ICS9DB803DGILF IDT, Integrated Device Technology Inc, ICS9DB803DGILF Datasheet - Page 7

• Manufacturer Part Number: ICS9DB803DGILF
• Description: IC BUFFER 8OUTPUT DIFF 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr
• Series: -r

Specifications of ICS9DB803DGILF

• Input: HCSL
• Output: HCSL, LVDS
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 200mA
• Pll Input Freq (min): 50MHz
• Pll Input Freq (max): 110MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: 50 to 100MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9DB803DGILF

Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
IDT
T
Operating Supply Current
1
2
3
Tambient
ESD prot
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Time from deassertion until outputs are >200 mV
Symbol
VDD_In
VDD_A
A
Modulation Frequency
Tcase
ICS9DB803DI
Eight Output Differential Buffer for PCIe for Gen 2
Tdrive_SRC_STOP#
TM
Powerdown Current
= -40 - 85°C; Supply Voltage V
Input High Voltage
Input High Current
V
V
Input Low Voltage
Ts
Input Low Current
/ICS
Input Frequency
Clk Stabilization
IL
IH
Pin Inductance
PLL Bandwidth
PARAMETER
Capacitance
Tdrive_PD#
TM
Trise
Eight Output Differential Buffer for PCIe Gen 2
Tfall
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
human body model
Input High Voltage
Case Temperature
Input Low Voltage
Parameter
SYMBOL
F
I
I
t
DD3.3OP
t
DD3.3PD
iBYPASS
T
DRVSTP
F
C
DRVPD
f
BW
V
L
C
V
I
I
MOD
STAB
I
iPLL
t
IL1
IL2
OUT
t
IH
pin
R
IH
IN
F
IL
DD
= 3.3 V +/-5%
stabilization or de-assertion of PD# to 1st
V
From V
IN
V
Rise time of PD# and SRC_STOP#
IN
Fall time of PD# and SRC_STOP#
= 0 V; Inputs with no pull-up resistors
PLL Bandwidth when PLL_BW=0
PLL Bandwidth when PLL_BW=1
= 0 V; Inputs with pull-up resistors
all differential pairs tri-stated
Full Active, C
DD
GND-0.5
SRC_Stop# de-assertion
Output pin capacitance
DIF output enable after
DIF output enable after
2000
Triangular Modulation
Min
Power-Up and after input clock
-65
-40
all diff pairs driven
PD# de-assertion
CONDITIONS
Bypass Mode
3.3 V +/-5%
3.3 V +/-5%
Logic Inputs
PLL Mode
V
IN
clock
= V
L
V
= Full load;
DD
DD
Max
150
115
4.6
4.6
+0.5V
85
7
Units
°
°C
°C
V
V
V
V
V
C
GND - 0.3
MIN
-200
1.5
0.7
50
50
30
-5
-5
2
2
TYP
3
1
ICS9DB803DI
V
DD
MAX
200
110
400
300
0.8
1.4
60
33
10
5
6
7
5
6
4
1
5
5
+ 0.3
UNITS NOTES
MHz
MHz
MHz
MHz
REV A 06/18/08
kHz
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
ns
us
ns
ns
V
V
1,2
1,3
1,3
1
1
1
1
1
1
1
1
1
2