ICS952906AFLF IDT, Integrated Device Technology Inc, ICS952906AFLF Datasheet - Page 16

• Manufacturer Part Number: ICS952906AFLF
• Description: IC TIMING CTRL HUB P4 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS952906AFLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 460MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 460MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 952906AFLF

Absolute Maximum Ratings
Core Operating Voltage . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Operating Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V
Lo gic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
1236A—08/06/07
T
Operating Supply Current
1
2
3
Electrical Characteristics - Input/Supply/Common Output Parameters
ppm frequency accuracy on PLL outputs.
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
A
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
Modulation Frequency
Powerdown Current
= 0 - 70°C; Supply Voltage V
Input Capacitance
Input High Voltage
Clk Stabilization
Input MID Voltage
Input High Current
Input Low Voltage
Input Low Current
Input Frequency
Pin Inductance
PARAMETER
Integrated
Circuit
Systems, Inc.
1,2
1
3
1
SYMBOL
I
I
DD3.3OP
DD3.3PD
T
C
V
C
L
V
V
I
I
C
STAB
I
DD
IL1
IL2
F
OUT
MID
IH
pin
INX
IH
IL
IN
i
= 3.3 V +/-5%
assertion of PD# to 1st clock.
V
V
all differential pairs tri-stated
From VDD Power-Up or de-
IN
Full Active, C
IN
Output pin capacitance
= 0 V; Inputs with no pull-
= 0 V; Inputs with pull-up
Triangular Modulation
all diff pairs driven
CONDITIONS
X1 & X2 pins
Logic Inputs
up resistors
V
3.3V +/-5%
3.3V +/-5%
3.3V +/-5%
V
resistors
DD
IN
= 3.3 V
= V
L
= Full load;
DD
16
DD
+ 0.5 V
V
SS
MIN
-200
30
-5
-5
2
1
-0.3
14.31818
TYP
V
DD
MAX
350
1.8
0.8
1.8
35
12
33
5
7
5
6
5
+ 0.3
ICS952906A
UNITS NOTES
MHz
kHz
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
pF
V
V
V
1,2
3
1
1
1
1
1