ICS954204BGLF IDT, Integrated Device Technology Inc, ICS954204BGLF Datasheet - Page 3

• Manufacturer Part Number: ICS954204BGLF
• Description: IC TIMING CTRL HUB P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS954204BGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 954204BGLF

Pin Description (Continued)
0933D—03/16/05
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
*Pins 32 and 33 have pull-ups.
PIN # PIN NAME
GND
SRCCLKC5
SRCCLKT5
CLKREQB#*
CLKREQA#*
VDDSRC
CPUCLKC2_ITP/SRCCLKC7
CPUCLKT2_ITP/SRCCLKT7
VDDA
GNDA
IREF
CPUCLKC1
CPUCLKT1
VDDCPU
CPUCLKC0
CPUCLKT0
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
FSLC/TEST_SEL
CPU_STOP#
PCI/SRC_STOP#
PCICLK2
Integrated
Circuit
Systems, Inc.
Type
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
Pin Description
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Supply for SRC clocks, 3.3V nominal
Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required for
voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
PCI clock output.
3.3V tolerant input for CPU frequency selection. Low voltage threshold
3
ICS954204