ICS94211AF IDT, Integrated Device Technology Inc, ICS94211AF Datasheet

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ICS94211AF

Manufacturer Part Number
ICS94211AF
Description
IC FREQ GENERATOR PROGR 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS94211AF

Input
Crystal
Output
Clock
Frequency - Max
332MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
332MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
94211AF

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ICS94211AF
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20 000
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ICS94211AFLF-T
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Programmable System Frequency Generator for PII/III™
Recommended Application:
440BX/VIA Apollo Pro133/ ALI 1631 style chipset.
Output Features:
Features:
Key Specifications:
Block Diagram
PCI_STOP#
0441F—08/24/05
BUFFER IN
FS(3:0)
MODE
SDATA
SCLK
2 - CPUs @2.5V
1 - IOAPIC @ 2.5V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCICLK, PCICLK_F,
SDRAM skew.
Real time system reset output
Spread spectrum for EMI control typically by 7dB to
8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
CPU – CPU: <175ps
SDRAM - SDRAM: <500ps
PCI – PCI: <500ps
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
X2
X1
4
Integrated
Circuit
Systems, Inc.
XTAL
OSC
Spectrum
PLL2
Spread
PLL1
Control
Config.
Logic
Reg.
DIVDER
CLOCK
PCI
STOP
/2
13
5
2
2
48MHz
24MHz
IOAPIC
SDRAM (12:0)
PCICLK (4:0)
PCICLK_F
CPUCLK (1:0)
RESET#
REF(1:0)
Functionality
*MODE/PCICLK_F
*PCI_STOP/REF0
F
**FS3/PCICLK0
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SDRAM12_F
*
** Internal Pull-down resistor of 120K to GND
BUFFER_IN
3
SDRAM11
SDRAM10
VDDSDR
PCICLK1
PCICLK2
PCICLK3
PCICLK4
SDRAM9
VDDREF
Internal Pull-up Resistor of 120K to VDD
VDDPCI
VDDPCI
SDATA
F
SCLK
GND
GND
GND
GND
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X1
X2
2
48-Pin 300mil SSOP
Pin Configuration
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
1
2
3
4
5
6
7
8
9
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
(
6
8
7
8
6
C
M
0
0
2
1
0
0
4
5
2
3
1
6
0
5
3
8
3
0
0
5
0
0
4
2
4
9
P
2
H
0 .
0 .
8 .
3 .
0 .
0 .
2 .
0 .
9 .
9 .
0 .
0 .
0 .
0 .
9 .
0 .
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
U
) z
0
0
2
1
1
ICS94211
0
3
0
9
9
0
0
0
0
9
1
VDDLAPIC
IOAPIC
REF1/FS2*
GND
CPUCLK0
CPUCLK1
VDDLCPU
RESET#
SDRAM0
GND
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
GND
SDRAM5
SDRAM6
VDDSDR
SDRAM7
SDRAM8
VDD48
48MHz/FS0*
24MHz/FS1*
P
(
C
4
3
4
3
3
4
3
3
3
3
3
3
3
3
3
3
M
0
7
1
4
7
0
8
6
5
5
7
1
3
3
4
3
C I
H
0 .
5 .
6 .
3 .
3 .
0 .
3 .
6 .
0 .
0 .
5 .
0 .
2 .
4 .
0 .
4 .
) z
L
0
0
5
3
4
0
3
6
0
0
0
0
5
1
1
1
K

Related parts for ICS94211AF

ICS94211AF Summary of contents

Page 1

Integrated Circuit Systems, Inc. Programmable System Frequency Generator for PII/III™ Recommended Application: 440BX/VIA Apollo Pro133/ ALI 1631 style chipset. Output Features: • CPUs @2.5V • IOAPIC @ 2.5V • SDRAM @ 3.3V • 6 ...

Page 2

ICS94211 General Description The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary clock signals for such a system. The ICS94211 belongs to ICS new generation of programmable ...

Page 3

General I C serial interface information for the ICS94211 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command ...

Page 4

ICS94211 Brief I Programmable System Frequency Generator Register Name Functionality & Frequency Select Register Output Control Registers Vendor ID & Revision ID Registers Byte Count Read Back Register Watchdog Timer Count Register Watchdog Control Registers VCO Control Selection Bit VCO ...

Page 5

Byte 0: Functionality and frequency select register (Default= ...

Page 6

ICS94211 Byte 1: CPU, Active/Inactive Register (1= enable disable ...

Page 7

Byte 7: Vendor ID and Revision ID Register ...

Page 8

ICS94211 Byte 13: Spread Sectrum Control Register ...

Page 9

Byte 19: Reserved Register ...

Page 10

ICS94211 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . ...

Page 11

Electrical Characteristics - CPU 70°C;VDD = 3.3V DDL PARAMETER SYMBOL 1 Output Impedance R DSP2B 1 Output Impedance R DSN2B Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I ...

Page 12

ICS94211 Electrical Characteristics - IOAPIC 70°C; VDD = 3.3V DDL PARAMETER SYMBOL 1 Output Impedance R DSP4B 1 Output Impedance R DSN4B Output High Voltage V OH4B Output Low Voltage V OL4B Output High ...

Page 13

Electrical Characteristics - REF, 24_48MHz, 48MHz 70° 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP5 1 Output Impedance R DSN5 Output High Voltage V OH5 Output Low Voltage V ...

Page 14

ICS94211 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS94211 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 15

PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS94211 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94211 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# ...

Page 16

ICS94211 INDEX INDEX AREA AREA 45° 45° .10 (.004) C .10 (.004) C Ordering Information ICS94211yFLF-T Example: ICS XXXX ...

Page 17

Revision History Rev. Issue Date Description F 8/24/2005 Added LF Ordering Information. 0441F—08/24/05 17 ICS94211 Page # 16 ...

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