CY2313ANZSC-1 Cypress Semiconductor Corp, CY2313ANZSC-1 Datasheet - Page 2

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CY2313ANZSC-1

Manufacturer Part Number
CY2313ANZSC-1
Description
IC CLK BUFF 13OUT SDRAM 28SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Clock Bufferr
Datasheet

Specifications of CY2313ANZSC-1

Package / Case
28-SOIC (7.5mm Width)
Frequency - Max
100MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
100MHz
Number Of Outputs
13
Max Input Freq
100 MHz
Propagation Delay (max)
5 ns
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Output
-
Input
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2313ANZSC-1
Quantity:
453
Pin Summary
Serial Configuration Map
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enabled
Document #: 38-07144 Rev. *B
V
V
V
V
BUF_IN
SDATA
SCLK
SDRAM [0-12]
Bit 7 11
Bit 6 10
Bit 5 --
Bit 4 --
Bit 3 7
Bit 2 6
Bit 1 3
Bit 0 2
• The Serial bits will be read by the clock driver in the following
• Reserved and unused bits should be programmed to “0”
• Serial interface address for the CY2313ANZ is:
Bit
Name
DD
SS
DDIIC
SSIIC
order:
A6
1
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Pin #
A5
1
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Reserved, drive to 0
Reserved, drive to 0
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
A4
0
Pins
1, 5, 20, 24, 28
4, 8, 17, 21, 25
13
16
9
14
15
2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23,
26, 27
A3
1
Description
A2
0
A1
0
A0
1
R/W
----
3.3V Digital voltage supply
Ground
Serial interface voltage supply
Ground for serial interface
Input clock
Serial data input, internal pull-up to V
Serial clock input, internal pull-up to V
SDRAM clock outputs
Description
Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
27
26
23
22
--
--
19
18
--
12
--
--
--
--
--
--
Pin #
Pin #
Reserved, drive to 0
SDRAM12 (Active/Inactive)
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
Reserved, drive to 0
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
Reserved, drive to 0
Reserved, drive to 0
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
DD
DD
Description
Description
CY2313ANZ
Page 2 of 8

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