LMX2512LQX0967 National Semiconductor, LMX2512LQX0967 Datasheet - Page 8

• Manufacturer Part Number: LMX2512LQX0967
• Description: IC SYNTHESIZER PLL VCO 28-LLP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: Frequency Synthesizer (RF/IF), Korean CDMA, Cellularr

Specifications of LMX2512LQX0967

• Output: LVCMOS
• Frequency - Max: 979MHz
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-LLP
• Frequency-max: 979MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Input: -

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Functional Description
X = Don’t care.
LOCK DETECT
The LD output can be used to indicate the lock status of the
RF PLL. Bit 21 in Register R0 determines the signal that
appears on the LD pin. When the RF PLL is not locked, the
Note 9: LD output becomes LOW when the phase error is larger than t
Note 10: LD output becomes HIGH when the phase error is less than t
four or more consecutive cycles.
Note 11: Phase Error is measured on leading edge. Only errors greater than
t
W1
CE Pin
and t
0
1
1
1
1
W2
TABLE 2. Power Down Configuration
are labeled.
RF_EN
X
0
0
1
1
IF_EN
FIGURE 1. Lock Detect Timing Diagram Waveform (Notes 9, 10, 11, 12, 13)
X
0
1
0
1
RF Circuitry
OFF
OFF
OFF
ON
ON
(Continued)
IF Circuitry
OFF
OFF
OFF
ON
ON
W1
W2
for
.
8
LD pin remains LOW. After obtaining phase lock, the LD pin
will have a logical HIGH level. The output can also be
programmed to be ground at all times.
Note 12: t
Note 13: The lock detect comparison occurs with every 64
f
N
.
RF PLL Section
W1
LD Bit
Not Locked
and t
0
1
Locked
TABLE 3. Lock Detect Modes
TABLE 4. Lock Detect Logic
W2
are equal to 10 ns.
Disable (GND)
Enable
Mode
LD Output
HIGH
LOW
20068005
th
cycle of f
R
and