PI6CU877NFE Pericom Semiconductor, PI6CU877NFE Datasheet - Page 7

• Manufacturer Part Number: PI6CU877NFE
• Description: IC PLL CLOCK DRIVER DDR2 52VFBGA
• Manufacturer: Pericom Semiconductor
• Type: PLL Clock Driverr

Specifications of PI6CU877NFE

• Input: SSTL-18
• Output: SSTL-18
• Frequency - Max: 270MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-VFBGA
• Frequency-max: 270MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Specifi cations
Switching char ac ter is tics over rec om mend ed operating free-air temperature range (unless oth er wise noted)
Notes:
11. Static Phase Offset does not include Jitter
12. Period Jitter and Half-Period Jitter specifi cations are separate specifi cations that must be met independently of each other.
13. VOX specifi ed at the DRAM clock input or the test load.
14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
Parameter
tjit(hper)
tjit(cc+)
t(Ø)dyn
tjit(per)
tjit(cc-)
tsk(o)
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For con sis ten cy, equal length cables should be used.
slr(o)
slr(i)
V
t(Ø)
tdis
ten
OX
08-0298
The PLL on the PI6CUx877 is capable of meeting all the above test parameters while supporting SSC synthesirers
OE to and Y/Y
OE to and Y/Y
Cycle-to-cycle jitter
Static phase offset
Dynamic phase offset
Output clock skew
Period jitter
Half period jitter
Half period jitter
Input clock slew rate
Output enable (OE)
Output clock slew rate
Outpu differential-pair cross voltage
SSC modulation frequency
SSC clock input frequency deviation
PLL Loop Bandwidth
PI6CUx877 PLL design should target the values below to minimize the SCC induced skew:
(12)
(12)
(12)
Description
(11)
160 to 270 MHz
271 to 360 MHz
(14, 16)
with the following parameters:
(13)
see Fig 4
see Fig 5
see Fig 10
see Fig 6
see Fig 7
see Fig 8
see Fig 8
see Fig 9
see Fig 9
see Fig 1, 9
see Fig 2
7
see Fig 11
see Fig 11
Diagram
(V
30.00
Min.
DDQ
0.00
-0.1
-50
-50
-40
-75
-50
0.5
1.5
2.0
0
0
1
AV
/2)
DD
, V
Nom.
DDQ
2.5
2.5
= 1.8 ±0.1V
PI6CU877, PI6CUA877
PLL Clock Driver for
(15)
1.8V DDR2 Memory
(V
Max.
-0.50
DDQ
+0.1
-40
40
50
50
40
40
75
50
33
PS8689G
8
8
4
3
/2)
Units
MHz
V/ns
kHz
ns
ps
%
V
01/17/06