SI5315A-C-GMR Silicon Laboratories Inc, SI5315A-C-GMR Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI5315A-C-GMR
Manufacturer Part Number
SI5315A-C-GMR
Description
IC CLK MULT 8KHZ-644.53MHZ 36QFN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5315B-C-GM.pdf
(58 pages)
Specifications of SI5315A-C-GMR
Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
36-VQFN
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2. System Level Overview
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and
generates two equal frequency, low jitter clock outputs ranging from 8 kHz to 644.53 MHz. For ease of use, the
Si5315 is pin controlled to enable simple device configuration of frequency plans, PLL loop bandwidth, and input
clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency
translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards. The Si5315 implements
internal state machines to control hitless switching between input clocks and holdover. Status alarms, loss of signal
(LOS) and loss of lock (LOL) are provided on output pins to indicate a change in device status.
This device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or
Ethernet backplane. The Si5315 synchronizes to backplane clocks and generates a multiplied, jitter attenuated
Ethernet/SONET/SDH clock or PDH clock. A typical system application is shown in Figure 5. The Si5315
translates a 19.44 MHz clock from the telecom backplane to an Ethernet or SONET/SDH clock frequency to the
PHY and filters the jitter to ensure compliance with related ITU-T and Telcordia standards.
BITS A
BITS B
Timing Cards
Hitless Switching
Wander Filtering
Redundant
Synchronization
Holdover
Network Sync
Network
PLL
19.44 MHz
25 MHz
8 kHz
Figure 5. Typical Si5315 Application
A
B
Backplane
Telecom
Ethernet
or
Rev. 0.26
A
B
A
B
Frequency Translation
Frequency Translation
Rx Timing Path
Rx Timing Path
Tx Timing Path
Tx Timing Path
Hitless Switching
Hitless Switching
Jitter Filtering
Jitter Filtering
19.44 MHz
19.44 MHz
SONET / SDH / PDH Line Card
Si5315
Si5315
25 MHz
25 MHz
8 kHz
8 kHz
SyncE Line Card
10G LAN / WAN
Multi-Port
155.52 MHz
156.25 MHz
161.1328125 MHz
77.76 / 155.52 MHz
1.544 / 2.048 MHz
OC-3 / 12
10GbE
10GbE
T1 / E1
PHY
PHY
Recovered
Recovered
Clocks
Clocks
Line
Line
Si5315
15