SI5367A-C-GQR Silicon Laboratories Inc, SI5367A-C-GQR Datasheet - Page 3
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SI5367A-C-GQR
Manufacturer Part Number
SI5367A-C-GQR
Description
IC CLOCK MULTIPLIER PROG 100TQFP
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5367C-C-GQR.pdf
(18 pages)
Specifications of SI5367A-C-GQR
Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI5367A-C-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Table 1. Performance Specifications (Continued)
(V
Table 2. Absolute Maximum Ratings
Duty Cycle Uncertainty
PLL Performance
Jitter Generation
Jitter Transfer
Phase Noise
Subharmonic Noise
Spurious Noise
Package
Thermal Resistance
Junction to Ambient
Notes:
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ), Except CKIN Pins
ESD HBM Tolerance (100 pF, 1.5 kΩ), CKIN Pins
ESD MM Tolerance, Except CKIN Pins
ESD MM Tolernace, CKIN Pins
Latch-Up Tolerance
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
DD
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
= 1.8 ±5% or 2.5 V ±10%, T
Family Reference Manual. This document can be downloaded from
Documentation).
Manual. In most designs an external resistor voltage divider is recommended.
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Parameter
Parameter
Symbol
SP
SP
CKO
CKO
J
A
J
θ
GEN
SUBH
SPUR
= –40 to 85 ºC)
PK
JA
DC
PN
Differential 100 Ω Line-to-Line Mea-
Phase Noise @ 100 kHz Offset
(n > 1, n x F3 < 100 MHz)
f
f
IN
IN
LVPECL output format
Max spur @ n x F3
sured at 50% point
= f
= f
Preliminary Rev. 0.4
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
Test Condition
100 kHz offset
OUT
100 Hz offset
10 kHz offset
OUT
1 MHz offset
1 kHz offset
LVPECL
Still Air
= 622.08 MHz,
= 622.08 MHz
Symbol
T
V
T
V
STG
JCT
DIG
DD
www.silabs.com/timing
–0.3 to (V
Min
–40
—
—
—
—
—
—
—
—
—
—
—
—
–0.5 to 3.6
–55 to 150
–55 to 150
JESD78 Compliant
Value
700
200
150
2
DD
TBD
0.05
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ
0.6
0.6
40
—
+ 0.3)
(click on
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.1
40
Si5367
—
Unit
ºC
ºC
kV
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps rms
ps rms
ps rms
V
V
V
V
V
ºC/W
Unit
dBc
dBc
dB
ps
3