SI5367A-C-GQ Silicon Laboratories Inc, SI5367A-C-GQ Datasheet - Page 2

• Manufacturer Part Number: SI5367A-C-GQ
• Description: IC CLOCK MULTIPLIER PROG 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5367A-C-GQ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5367
Table 1. Performance Specifications
(V
2
Temperature Range
Supply Voltage
Supply Current
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4,
CKOUT5)
3-Level Input Pins
Input Mid Current
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing CKN
Common Mode Voltage
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5)
Common Mode
Differential Output Swing
Single Ended Output
Swing
Rise/Fall Time
Notes:
DD
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
= 1.8 ±5% or 2.5 V ±10%, T
Family Reference Manual. This document can be downloaded from
Documentation).
Manual. In most designs an external resistor voltage divider is recommended.
Parameter
CKN
CKO
Symbol
CKN
CKN
CK
V
A
V
CK
I
V
V
I
IMM
OCM
T
DD
= –40 to 85 ºC)
OD
DD
SE
A
OF
VCM
DPP
TRF
TRF
F
DC
cation ratio determined by program-
given input frequency/clock multipli-
ming device PLL dividers. Consult
Precision Clock Family Reference
(click on Documentation) to deter-
Input frequency and clock multipli-
Silicon Laboratories configuration
Manual at
software DSPLLsim or Any-Rate
mine PLL divider settings for a
cation ratio combination.
Only CKOUT1 enabled
Only CKOUT1 enabled
LVPECL format output
All CKOUTs enabled
All CKOUTs enabled
CMOS format output
Whichever is smaller
Tristate/Sleep Mode
f
OUT
f
Preliminary Rev. 0.4
OUT
Test Condition
www.silabs.com/timing
See Note 2.
2.5 V ±10%
100 Ω load
1.8 V ±5%
line-to-line
= 622.08 MHz
LVPECL
20–80%
20–80%
= 19.44 MHz
www.silabs.com/timing
V
DD
1213
2.25
1.71
0.25
Min
–40
970
0.9
1.0
1.1
0.5
10
10
–2
40
—
—
—
—
—
—
– 1.42
2
TBD
Typ
394
253
278
229
230
2.5
1.8
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(click on
V
DD
707.35
1417
1134
Max
2.75
1.89
TBD
0.93
435
284
321
261
945
350
1.9
1.4
1.7
1.9
85
60
11
2
– 1.25
MHz
MHz
Unit
V
mA
mA
mA
mA
mA
µA
ºC
ns
ns
ps
%
V
V
V
V
V
V
V
PP