FPD85310VJD National Semiconductor, FPD85310VJD Datasheet - Page 7

• Manufacturer Part Number: FPD85310VJD
• Description: IC CTRLR PANEL TIMING 100-TQFP
• Manufacturer: National Semiconductor
• Type: Panel Timing Controllerr

Specifications of FPD85310VJD

• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency-max: -
• Output: -
• Input: -
• Other names: *FPD85310VJD

Functional Description
FPD-LINK RECEIVER
The LVDS based FPD-Link Receiver receives inputs video
data and control timing. Four LVDS channels plus clock pro-
vide 24-bit color. Three LVDS channels can be used for
18-bit color.
The video data is regenerated to a parallel data stream and
routed to the 8 to 6 Bit Translator. When SPDZ is active (low)
the FPD85310 is placed in a power down mode. The Gen-
eral Purpose Outputs (GPOs) continue outputting the pro-
grammed control sequence at a reduced frame rate. RSTZ
initialized the chip with the default register values. EEPROM
configuration data is loaded if EEPROM is detected. (EE-
PROM address 80H = “00”).
8 to 6 Bit Translator
8-bit data is reduced to a 6-bit data path via a time multi-
plexed dithering technique or a simple truncation of the
LSBs. This function is enabled via the Input Control Register
bits 4 and 3. See Table 2 Input Format Control register.
DATA ALIGNMENT
This function delays and aligns data to match the CD/panel
architect. The following programmable selections in the Out-
put Format Control Register bits 0 and 1 provide support for
various panel architectures. See Figures 10, 11, 12, 13, 14
for additional explanation.
Dual Bus, Single Port CD Interface
When interfacing two busses to a bank of single port column
drivers, the RGB data must be aligned/delayed with respect
to the size of the column drivers being used. The CD Size
register is programmed to support single port column drivers
of up to 384 outputs (128 pixels).
Dual Bus, Dual Port CD Interface
When interfacing with dual port column drivers, data is sim-
ply output with odd and even data on separate outputs.
Single Bus, Single Port CD Interface
The single bus, single port column driver interface provides
support of existing SVGA systems. All data is output on a
single bus. The second bus can be turned off when using
this configuration.
Output Formatting
The output formatting function provides several capabilities
to reduce noise EMI and to generate customized timing.
These capabilities are selectable/programmable via the Out-
put Format Control, Output Enable/Polarity Control, and Out-
put Drive Control Registers. See Table 2 for specific bit defi-
nitions.
Data Bus Skewing
This function aligns the two output channels in either a non-
skewed data format (simultaneous switching) or a skewed
data format. The skewed format delays the even channel
data and control by
puts which switch simultaneously. See Figures 10, 11, 12,
13, 14 . Data Bus Skewing is enabled by setting bit 2 in the
Output Format Control register.
1
⁄
2
clock. This reduces the number of out-
7
Programmable Skew Rates
Programmable edge rates allow the Data, Polarity, Start
Pulse, and Clock outputs to be adjusted for better imped-
ance matching for noise and EMI reduction. Bits [7:6] of the
Output Enable/Polarity Control Register control OSP and
ESP outputs. The Output Drive Control register control the
OCLK, ECLK, ORGB/OPOL, ERGB/EPOL outputs.
Polarity Generation
When enabled, a polarity indication is output for each data
bus. If the number of transitions from pixel to pixel exceed 18
bits from 36 bits, the data is inverted and a polarity indication
corresponding to that bus is set active. This requires the use
of a CD with a polarity input and in “SKEWED” mode, OPOL
and EPOL are separated for each skewing then two port CD
need to be two polarity inputs. Polarity Generation is not sup-
ported in the single bus/single port CD configuration (SVGA
configuration). The polarity function is enabled by setting bit
6 of the Output Format Control register (EEPROM address
D2). The OCLK and ECLK polarity is also programmable. In-
version and TRI-STATE control of OCLK and ECLK is pro-
vided by bits [3:0] of the Output Enable/Polarity Control Reg-
ister. The ERGB/ESP/EPOL and ORGB/OSP/OPAL outputs
can be disabled (TRI-STATE) using bits [5:4] of the Output
Enable/Polarity Control register.
Programmable Positioning of CD Start Pulse
The position of the CD Start Pulse is programmable. This al-
lows use with column drivers having non-standard start
pulse timing. The CD Start Pulse position is determined by
bits [3:0] of the Output Format Control Register (EEPROM
address D3).
Data Blanking
Data, Polarity, Start Pulse and Clock can be blanked (forced
to “0”) during horizontal and/or vertical blanking periods.
GPO [8] is programmed to correspond to display periods.
When GPO [8] is low, outputs are forced to “0”. This reduces
amount of switching over the frame time thus reducing
power. See GPO programming procedure in APPENDIX A:
GPO Programming Examples .
Line Inversion
When enabled (Bit 3 of the Output Format Register), the po-
larity of the output data is determined by GPO [0]. Bit 4 de-
fines the relationship between GPO [0] and the output data.
Bit 5 provides a variation of this where the Odd and Even
data is of different polarity. This could be used in a system
with CDs on both top and bottom of the panel in which dot in-
version is desired.
White Data
The White Data function generates all “1” data beginning at
line 769 and continuing until the beginning of the next frame.
This function is controlled via D6 Register Bit 7.
Timing Control
The Timing Control function generates control to column
drivers, row drivers, and power supply. The programmable
GPOs provide for CD latch pulse, REV, and gate driver con-
trol generation. The GPOs allow the user to generate control
anywhere within the frame data. Standard gate driver inter-
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