SY100EP15VK4G Micrel Inc, SY100EP15VK4G Datasheet - Page 7

• Manufacturer Part Number: SY100EP15VK4G
• Description: IC BUFFER FAN 1:4 3.3/5V 16TSSOP
• Manufacturer: Micrel Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: 100EP, Precision Edge®, ECL Pro™r

Specifications of SY100EP15VK4G

• Number Of Circuits: 1
• Ratio - Input:output: 4:4
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVECL, LVPECL
• Output: LVECL, LVPECL
• Frequency - Max: 2.5GHz
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 2.5GHz
• Frequency: 2.5GHz
• No. Of Outputs: 4
• Supply Current: 52mA
• Supply Voltage Range: ± 2.97V To ± 3.63V, ± 4.5V To ± 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Number Of Clock Inputs: 2
• Operating Supply Voltage (min): -2.97/2.97V
• Operating Supply Voltage (typ): -3.3/-5/3.3/5V
• Operating Supply Voltage (max): -5.5/5.5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1992-5; SY100EP15VK4G

Micrel, Inc.
LVPECL: V
ECL: V
Notes:
1. f
2. Skew is measured between outputs under identical transitions.
3. Set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. For asynchronous applications,
4. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
5. Total jitter definition: with an ideal clock input applied to one channel of the MUX, no more than one output edge in 10
M9999-120505
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Symbol
f
t
t
t
t
t
V
t
MAX
PD
SKEW
S
H
JITTER
r
AC ELECTRICAL CHARACTERISTICS
, t
ID
50Ω to V
set-up and hold time does not apply.
where T is the time between rising edges of the output signal.
more than the specified peak-to-peak jitter value.
(3)
(3)
MAX
f
(1)
(2)
is defined as the maximum toggle frequency. Measured with 750mV input signal, 50% duty cycle, output swing ≥ 400mV(diff), all loading with
CC
CC
= 0V, V
Maximum Frequency
PropagationDelay to Output
PECL/ECL
LVPECL/LVECL
Within-Device Skew
Part-to-Part Skew
Set-Up Time
Hold Time
Cycle-to-Cycle Jitter
Total Jitter (622MHz clock)
Input Voltage Range
Output Rise/Fall Times
(20% to 80%)
CC
–2V.
= 2.97V to 3.63V, V
EE
IN (Single-Ended)-to-Q
IN (Single-Ended)-to-Q
= –4.5V to –5.5V; LVECL: V
Parameter
(4)
Diff. IN-to-Q
Diff. IN-to-Q
/EN to CLK
/EN to CLK
SEL-to-Q
SEL-to-Q
EE
(5)
(Diff.)
(Diff.)
= 0V; PECL: V
Min.
275
250
250
275
250
250
100
200
150
2.5
75
—
—
—
—
T
CC
A
= –40
Typ.
CC
<20
800
= 0V, V
0.2
50
—
—
—
—
—
—
—
—
—
—
0
= 4.5V to 5.5V, V
°
C
7
EE
Max.
1200
425
450
450
425
450
450
150
225
25
—
—
—
—
1
= –2.97V to –3.63V
Min.
275
250
250
275
250
250
100
200
150
2.5
75
—
—
—
—
EE
T
A
= 0V
= +25
Typ.
375
400
400
375
400
400
100
<20
800
130
0.2
15
50
—
0
°
C
Max.
1200
425
450
450
425
450
450
150
225
25
—
—
—
—
1
Min.
275
250
250
275
250
250
100
200
150
2.5
—
—
—
—
85
12
T
output edges will deviate by
A
= +85
Typ.
<20
800
0.2
50
—
—
—
—
—
—
—
—
—
—
0
JITTER_CC
°
C
Max.
1200
SY100EP15V
425
450
450
425
450
450
150
225
25
—
—
—
—
1
ECL Pro™
= T
n
–T
ps
ps
Unit
GHz
mV
n+1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
RMS
PP