ICS83023AMILF IDT, Integrated Device Technology Inc, ICS83023AMILF Datasheet - Page 5

• Manufacturer Part Number: ICS83023AMILF
• Description: XLATOR/BUFFER DUAL 1:1 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Translatorr

Specifications of ICS83023AMILF

• Number Of Circuits: 2
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/No
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 350MHz
• Number Of Outputs: 2
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 2.4ns
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 8
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOIC N
• Duty Cycle: 57%
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1102; 800-1102-5; 800-1102; 83023AMILF

83023AMI
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
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0
1k
10k
A
O
DDITIVE
FFSET
100k
F
www.idt.com
D
ROM
IFFERENTIAL
P
C
HASE
5
ARRIER
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
J
F
ITTER
REQUENCY
1M
-
TO
Additive Phase Jitter
-LVCMOS T
(H
Z
)
10M
(12kHz to 20MHz)
= 0.14ps typical
RANSLATOR
@ 100MHz
ICS83023I
D
UAL
REV. B JULY 29, 2010
100M
/B
, 1-
UFFER
TO
-1