ICS8305AGLF IDT, Integrated Device Technology Inc, ICS8305AGLF Datasheet - Page 2

• Manufacturer Part Number: ICS8305AGLF
• Description: IC CLK FAN BUFF MUX 2:4 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8305AGLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1110; 800-1110-5; 800-1110; 8305AGLF

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
Symbol
C
R
R
C
R
10, 12, 14, 16
ICS8305
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
IN
PULLUP
PULLDOWN
PD
OUT
Number
1, 9, 13
11, 15
2
3
4
5
6
7
8
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Q3, Q2, Q1, Q0
LVCMOS_CLK
CLK_SEL
CLK_EN
Name
nCLK
V
GND
CLK
V
OE
DDO
DD
Output
Power
Power
Power
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup/
Pullup
Pullup
Pullup
Test Conditions
Description
Power supply ground
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Power supply pin.
Synchronizing clock enable. When LOW, the output clocks are disabled.
When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,
selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7
LVCMOS/LVTTL interface levels.
Output supply pins.
2
Minimum
Ω
output impedance.
ICS8305AG REV. C OCTOBER 23, 2008
Typical
51
51
11
7
4
Maximum
Units
k
k
pF
pF
Ω
Ω
Ω