ICS85311AMLF IDT, Integrated Device Technology Inc, ICS85311AMLF Datasheet - Page 9

• Manufacturer Part Number: ICS85311AMLF
• Description: IC FANOUT BUFF LVPECL/ECL 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS85311AMLF

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: ECL, LVPECL
• Frequency - Max: 1GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 1GHz
• Number Of Outputs: 4
• Operating Supply Voltage (max): -3.465/3.465V
• Operating Temp Range: 0C to 70C
• Propagation Delay Time: 1.4ns
• Operating Supply Voltage (min): -2.375/2.375V
• Mounting: Surface Mount
• Pin Count: 8
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Package Type: SOIC N
• Duty Cycle: 52%
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1166; 800-1166-5; 800-1166; 85311AMLF

Recommendations for Unused Output Pins
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 3A. 3.3V LVPECL Output Termination
IDT™ / ICS™ LVPECL/ECL FANOUT BUFFER
ICS85311
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER
RTT =
((V
FOUT
OH
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
Z
o
50Ω
RTT
50Ω
V
CC
FIN
- 2V
9
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 3B. 3.3V LVPECL Output Termination
FOUT
Z
Z
o
o
= 50Ω
= 50Ω
ICS85311AM REV. D OCTOBER 22, 2008
125Ω
84Ω
3.3V
125Ω
84Ω
FIN