ICS8305AGILF IDT, Integrated Device Technology Inc, ICS8305AGILF Datasheet - Page 10

• Manufacturer Part Number: ICS8305AGILF
• Description: IC CLK FAN BUFF MUX 2:4 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8305AGILF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/No
• Input: HCSL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 350MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1947-5; 8305AGILF; ICS8305AGILF

IDT™ / ICS™ LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/ LVTTL FANOUT BUFFER
W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
8305AGI
IRING THE
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
I
F
NPUT TO
IGURE
Single Ended Clock Input
2. S
A
A
PPLICATION
www.icst.com/products/hiperclocks.html
CCEPT
INGLE
E
C1
0.1u
S
NDED
V_REF
INGLE
DD
LVCMOS-
/2 is
S
L
IGNAL
OW
E
10
10
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
S
1K
D
R1
1K
R2
KEW
RIVING
VDD
L
TO
EVELS
, 1-
CLK
nCLK
-LVCMOS/LVTTL F
D
IFFERENTIAL
TO
-4, M
I
NPUT
ULTIPLEXED
DD
= 3.3V, V_REF should be 1.25V
ANOUT
D
IFFERENTIAL
REV. B MAY 19, 2005
B
UFFER
ICS8305I
TSD
/