ICS83940DY-01LF IDT, Integrated Device Technology Inc, ICS83940DY-01LF Datasheet - Page 9

• Manufacturer Part Number: ICS83940DY-01LF
• Description: IC CLK FAN BUFF MUX 1:18 32LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS83940DY-01LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:18
• Differential - Input:output: Yes/No
• Input: CML, LVCMOS, LVPECL, LVTTL, SSTL
• Output: LVCMOS, LVTTL
• Frequency - Max: 250MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1923-2; 83940DY-01LF; ICS83940DY-01LF

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
R
I
CLK I
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
PCLK/nPCLK I
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can
be tied from PCLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
83940DY-01
NPUTS
ECOMMENDATIONS FOR
IRING THE
NPUT
:
:
ONTROL
D
NPUT
IFFERENTIAL
P
:
INS
:
U
NUSED
I
F
NPUT TO
IGURE
Single Ended Clock Input
I
1. S
NPUT AND
A
A
PPLICATION
CCEPT
INGLE
O
E
C1
0.1u
S
NDED
UTPUT
INGLE
V_REF
LVPECL-
DD
www.idt.com
/2 is
S
IGNAL
P
E
9
INS
I
NDED
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVCMOS O
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
D
1K
UTPUTS
R1
1K
R2
RIVING
TO
VDD
L
EVELS
-LVCMOS / LVTTL F
nPCLK
D
PCLK
:
UTPUT
IFFERENTIAL
:
I
NPUT
DD
= 3.3V, V_REF should be 1.25V
L
ICS83940-01
OW
S
ANOUT
KEW
REV. A AUGUST 4, 2010
, 1-
B
TO
UFFER
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