IDT5T9310NLGI IDT, Integrated Device Technology Inc, IDT5T9310NLGI Datasheet - Page 9

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IDT5T9310NLGI

Manufacturer Part Number
IDT5T9310NLGI
Description
IC CLK BUFF/DVR MUX 1:10 40VFQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Series
TERABUFFER™ IIr
Datasheet

Specifications of IDT5T9310NLGI

Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
Yes/Yes
Input
CML, eHSTL, HSTL, LVDS, LVEPECL, LVPECL, LVTTL
Output
LVDS
Frequency - Max
1GHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN, 40-VFQFPN
Frequency-max
1GHz
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
1000MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
40
Quiescent Current
295mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
5T9310NLGI
800-1985
IDT5T9310NLGI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT5T9310NLGI
Manufacturer:
IDT
Quantity:
125
Part Number:
IDT5T9310NLGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT5T9310NLGI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to V
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
A
asserting PD.
[1:2]
Qn - Qn
- A
[1:2]
GL
Gx
Qn - Qn
A
A
1
2
- A
- A
Gx
PD
1
2
t
PLH
Differential Gate Disable/Enable Showing Runt Pulse Generation
t
PGD
Power Down Timing
DD
. In the POWER DOWN TIMING diagram this is shown when Qn-Qn goes to V
9
t
PGE
INDUSTRIAL TEMPERATURE RANGE
+V
V
-V
+V
V
-V
V
V
V
V
V
V
+V
V
-V
DIF
DIF
IH
THI
IL
IH
THI
IL
DIF
DIF
DIF
DIF
DIF
DIF
DIF
=0
=0
=0
+ V
V
- V
V
V
V
V
V
V
+ V
V
- V
DIF
IH
THI
IL
IH
THI
IL
DIF
DIF
DIF
DIF
DIF
DIF
= 0
= 0
= 0.

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