CY2DP818ZC Cypress Semiconductor Corp, CY2DP818ZC Datasheet - Page 2

• Manufacturer Part Number: CY2DP818ZC
• Description: IC CLK FANOUT BUFFER 1:8 38TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Buffer (Distribution)r

Specifications of CY2DP818ZC

• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: Yes/Yes
• Input: LVDS, LVPECL, LVTTL
• Output: LVPECL
• Frequency - Max: 350MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Frequency-max: 350MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinouts
Pin Configuration
Pin Description
Table 1. Input Receiver Configuration for Differential or LVTTL/LVCMOS
Table 2. Single ended LVTTL/LVCMOS Input Logic (InConfig = 1)
Document #: 38-07061 Rev. *B
1, 9, 12, 18, 19, 20, 38
2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 VDD
10, 11
37, 36, 35, 34,
33, 32, 31, 30,
28, 27, 26, 25,
24, 23, 22, 21
7
Input A (+) Pin 10
InConfig (Pin 7)
Ground
Input
Input
VDD
Pin Number
1
0
LVTTL or LVCMOS
LVDS or LVPECL
Input Receiver Family
Input B (–) Pin 11
GND
Input A, Input B
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
InConfig
Ground
Input
Input
VDD
Pin Name
INPUT B
INPUT A
InConfig
GND
GND
VDD
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Figure 1. 38-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
POWER
POWER
Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
LVPECL
LVTTL/LVCMOS
Single ended, non-inverting or inverting, void of bias resistors
Differential, void of internal termination
Output Clock QnA Pins
Type
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
Invert
Invert
True
True
Q3B
Q8A
Q4B
VDD
Q5A
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q4A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8B
GND
Input Receiver Type
Ground
Power Supply
Clock Input. Either differential
LVPECL/LVDS or single-ended
LVTTL/LVCMOS, as determined by
InConfig. See
details.
Differential Output Clocks
Control Input. Selects input type: either
differential LVPECL/LVDS or
single-ended LVTTL/LVCMOS
See
Table 1
and
Description
Table 1
Table 2
and
CY2DP818
for details.
Table 2
Page 2 of 7
for
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