CY7B992-5JC Cypress Semiconductor Corp, CY7B992-5JC Datasheet - Page 13

• Manufacturer Part Number: CY7B992-5JC
• Description: CLOCK BUFFER CMOS OUT 32-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: RoboClock™r
• Type: Buffer/Driverr

Specifications of CY7B992-5JC

• Number Of Circuits: 1
• Ratio - Input:output: 8:8
• Differential - Input:output: Yes/Yes
• Input: 3-State, TTL
• Output: CMOS
• Frequency - Max: 80MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Frequency-max: 80MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1380

Operational Mode Descriptions
Figure 4
clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and each drives a
terminated transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency
range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with
impedances as low as 50 ohms), enables efficient printed circuit board design.
Figure 5
traces of different lengths. In addition to low skew between
outputs, the PSCB is programmed to stagger the timing of its
outputs. Each of the four groups of output pairs are programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is fed
Document Number: 38-07138 Rev. *E
SYSTEM
CLOCK
shows the PSCB configured as a zero skew clock buffer. In this mode the 7B991/992 is used as the basis for a low-skew
shows a configuration to equalize skew between metal
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 4. Zero Skew and Zero Delay Clock Driver
Figure 5. Programmable Skew Clock Driver
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
LENGTH L1 = L2 = L3 = L4
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LENGTH L1 = L2
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
L3 < L2 by 6 inches
L4 > L2 by 6 inches
REF
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
retarding the clock signal on shorter traces, all loads can receive
the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0-ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
L1
L2
L3
L4
L1
L2
L3
L4
Z
Z
Z
0
Z
0
Z
0
Z
Z
0
0
0
Z
0
0
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
CY7B991
CY7B992
Page 13 of 20
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