MPC962309EJ-1H IDT, Integrated Device Technology Inc, MPC962309EJ-1H Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
MPC962309EJ-1H
Manufacturer Part Number
MPC962309EJ-1H
Description
IC BUFFER ZD 1:5 3.3V 16-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet
1.MPC962305EF-1HR2.pdf
(17 pages)
Specifications of MPC962309EJ-1H
Pll
Yes with Bypass
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
1:9
Differential - Input:output
No/No
Frequency - Max
133.33MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
133.33MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IDT™ / ICS™ 3.3V ZERO DELAY BUFFER
MPC962305
LOW-COST, 3.3V ZERO DELAY BUFFER
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 1. Output-to-Output Skew t
Figure 3. Output Duty Cycle (DC)
Figure 5. Cycle-to-Cycle Jitter
t
t
2
N
t
1
t
N+1
DC = t
t
5
2
/t
1
x 100%
t
J
= |t
N
–t
APPLICATIONS INFORMATION
N+1
SK(O)
|
V
1.4 V
GND
CC
V
1.4 V
GND
V
1.4 V
GND
CC
CC
5
DEVICE 1
DEVICE 2
FB_IN
Figure 6. Output Transition Time Test Reference
CCLK
Figure 2. Static Phase Offset Test Reference
t
4
Figure 4. Device-to-Device Skew
t
6
t
7
MPC962305 REV 7 JULY 16, 2007
t
3
V
CC
2.0
= 3.3 V
0.8
V
V
GND
V
V
GND
CC
CC
CC
CC
V
V
GND
V
V
GND
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
÷ 2