IDT8535-01PGG8 IDT, Integrated Device Technology Inc, IDT8535-01PGG8 Datasheet
![IC FANOUT BUFFER LVPECL 20-TSSOP](/photos/31/27/312709/20pin_tssop_sml.jpg)
IDT8535-01PGG8
Specifications of IDT8535-01PGG8
Related parts for IDT8535-01PGG8
IDT8535-01PGG8 Summary of contents
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... LVCMOS-TO-3.3V LVPECL FANOUT BUFFER DESCRIPTION: The IDT8535- low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer. It has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL PIN CONFIGURATION CLK_EN 2 CLK_SEL 3 CLK0 CLK1 TSSOP TOP VIEW PIN DESCRIPTION (1) Symbol Number V 1 Power EE CLK_EN 2 Input CLK_SEL 3 Input CLK0 4 Input CLK1 6 Input Unused V 10, 13, 18 Power DD xQ3, Q3 11, 12 Output xQ2 Q2 14, 15 Output xQ1, Q1 16, 17 ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL NOTES: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table. ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL POWER SUPPLY CHARACTERISTICS - COMMERCIAL Symbol Parameter V Positive Supply Voltage DD I Power Supply Current EE DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL Symbol Parameter V Input Voltage HIGH IH V Input Voltage LOW CLK0, CLK1 IL CLK_EN, CLK_SEL I Input Current HIGH ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL POWER SUPPLY CHARACTERISTICS - INDUSTRIAL Symbol Parameter V Positive Supply Voltage DD I Power Supply Current EE DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - INDUSTRIAL Symbol Parameter V Input Voltage HIGH IH V Input Voltage LOW CLK0, CLK1 IL CLK_EN, CLK_SEL I Input Current HIGH ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL PARAMETER MEASUREMENT INFORMATION V DD LVPECL -1.3V ± 0.135V EE xQx Qx xQy Qy xQx Part 1 Qx xQy Part 2 Qy COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Z = 50Ω 50Ω xQx Output Load Test Circuit t SK(0) Output Skew t SK(PP) Part-to-Part Skew ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL PARAMETER MEASUREMENT INFORMATION - CONTINUED Clock Outputs CLK0, CLK1 xQ0, xQ1, xQ2, xQ3 Q0, Q1, Q2, Q3 xQ0, xQ1, xQ2, xQ3 Q0, Q1, Q2, Q3 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 80% 80% 20 Output Rise and Fall Time t PD Propagation Delay Pulse Width ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL APPLICATION INFORMATION TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. F and xF are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ...
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... This section provides information on power dissipation and junction temperature for the IDT8535-01. Equations and example calculations are also provided. POWER DISSIPATION: The total power dissipation for the IDT8535-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for the ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL CALCULATIONS AND EQUATIONS To calculate worst case power dissipation into the load, use the following equations, which assume a 50Ω load and a termination voltage of V For Logic HIGH OUT OH MAX DD MAX (V _ – MAX OH MAX For Logic LOW: V ...
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... IDT8535-01 LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL ORDERING INFORMATION IDT XXXXX XX X Package Process Device Type CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Commercial (0°C to +70°C) Blank Industrial (-40°C to +85° Thin Shrink Small Outline Package Low Skew, 1-to-4 LVCMOS-to-3 ...