ICS8533AG-01LFT IDT, Integrated Device Technology Inc, ICS8533AG-01LFT Datasheet - Page 8

• Manufacturer Part Number: ICS8533AG-01LFT
• Description: IC FANOUT BUFFER 1-4 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS8533AG-01LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8533AG-01LFT

W
8533AG-01
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
T
ERMINATION FOR
IRING THE
RTT =
F
((V
IGURE
FOUT
OH
+ V
D
3A. LVPECL O
OL
IFFERENTIAL
) / (V
1
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
F
I
IGURE
NPUT TO
Z
o
50
UTPUT
UTPUTS
2. S
T
A
RTT
ERMINATION
A
50
INGLE
CLK_IN
PPLICATION
CCEPT
V
0.1uF
CC
C1
E
FIN
- 2V
NDED
S
INGLE
CC
D
www.idt.com
S
/2 is
IGNAL
IFFERENTIAL
R1
1K
V_REF
R2
1K
E
8
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
D
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
RIVING
V
CC
+
-
L
EVELS
FOUT
F
D
IGURE
-
IFFERENTIAL
TO
-3.3V LVPECL F
3B. LVPECL O
Z
Z
I
o
o
NPUT
= 50
= 50
CC
125
= 3.3V, V_REF should be 1.25V
84
UTPUT
L
ICS8533-01
OW
3.3V
125
84
T
ANOUT
S
ERMINATION
KEW
REV. F AUGUST 4, 2010
FIN
, 1-
B
UFFER
TO
-4