ICS85310AYI-01LF IDT, Integrated Device Technology Inc, ICS85310AYI-01LF Datasheet - Page 8

• Manufacturer Part Number: ICS85310AYI-01LF
• Description: IC FANOUT BUFFER 1-10 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85310AYI-01LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: ECL, LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 2.375 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85310AYI-01LF

ICS5310I-01 Data Sheet
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
0.609.
Recommendations for Unused Input Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
Single-ended LVPECL Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
ICS85310AYI-01 REVISION I JANUARY 25, 2010
CC
= 3.3V, V_REF should be 1.25V and R2/R1 =
CC
/2 is
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL FANOUT BUFFER
8
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Figure 1. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
C1
0.1u
V_REF
©2010 Integrated Device Technology, Inc.
R1
1K
R2
1K
V
CC
CLKx
nCLKx