MPC9443AE IDT, Integrated Device Technology Inc, MPC9443AE Datasheet - Page 6
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MPC9443AE
Manufacturer Part Number
MPC9443AE
Description
IC CLK FANOUT BUFFER 48-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet
1.MPC9443AER2.pdf
(14 pages)
Specifications of MPC9443AE
Number Of Circuits
1
Ratio - Input:output
3:16
Differential - Input:output
Yes/No
Input
LVCMOS, LVPECL
Output
LVCMOS
Frequency - Max
350MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Frequency-max
350MHz
Number Of Clock Inputs
3
Output Frequency
350MHz
Output Logic Level
LVCMOS
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
LVCMOS/LVPECL
Mounting
Surface Mount
Pin Count
48
Quiescent Current
2mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC9443AE
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
MPC9443AER2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Table 9. DC Characteristics (V
Table 10. AC Characteristics (V
IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER
t
1. V
2. Input pull-up / pull-down resistors influence input current.
3. The MPC9443 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
4. I
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
4. t
5. Device-to-device skew referenced to the rising output edge.
6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.
7. Output pulse skew is the absolute difference of the propagation delay times: | t
Symbol
Symbol
sk(LH, HL)
V
V
t
I
t
t
PLZ, HZ
PZL, LZ
t
MPC9443
2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
CCQ
t
Z
P, REF
CMR
CMR
t
sk(PP)
f
DC
V
t
t
t
t
SK(P)
V
V
V
S
t
t
V
V
and the input swing lies within the V
transmission line to a termination voltage of V
V
MAX
and the input swing lies within the V
pulse width, output duty cycle and maximum frequency specifications.
f
PLH
PHL
PLH
PHL
I
OUT
r
r
CCQ
sk(LH, HL)
ref
, t
PP
IN
OH
OL
PP
, t
, t
IH
IL
CMR
CC
CMR
Q
(4)
f
H
f
(1)
(2)
= 2.5 V.
is the DC current consumption of the device with all outputs open and the input in its default state or open.
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Common Mode Range
Input Current
Output High Voltage
Output Low Voltage
Output Impedance
Maximum Quiescent Supply Current
Input Frequency
Maximum Output Frequency
Peak-to-Peak Input Voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation Delay
Output Disable Time
Output Enable Time
Setup, Hold Time (reference clock to CLK_STOP)
Output-to-Output Skew
Device-to-Device Skew (LH)
Device-to-Device Skew (LH, HL)
Output Pulse Skew
Output Duty Cycle
Output Rise/Fall Time
includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
(2)
Characteristics
Characteristics
f
Any output, same output divider
Q
(7)
<140 MHz and using PCLK0,1
Any output, any output divider
f
Q
(4)
<140 MHz and using CCLK
CC
CC
= V
PP
PP
(5)
= V
(DC) specification.
(AC) specification.
CCA
CCA
(6)
PCLK0,1 to any Q
PCLK0,1 to any Q
Within one bank
Using PCLK0,1
Using PCLK0,1
Using PCLK0,1
CCLK to any Q
CCLK to any Q
= V
TT
= V
Using CCLK
Using CCLK
Using CCLK
. Alternatively, the device drives up to one 50 Ω series terminated transmission line at
CCB
PCLK0, 1
PCLK0, 1
CCB
÷1 output
÷2 output
PCLK0,1
PCLK0,1
= V
= V
CCC
CCC
= V
= V
–0.3
Min
Min
250
500
500
CCD
1.7
1.1
1.8
1.3
1.4
2.5
2.4
2.1
1.9
0.1
45
45
TT
0
0
0
CCD
.
= 2.5 V ± 5%, T
6
= 2.5 V ± 5%, T
PLH
Typ
Typ
22
50
50
– t
PHL
A
|
A
= –40 to +85°C)
V
V
V
= –40 to +85°C)
CC
CC
CC
Max
1.0
1000
200
0.7
0.6
3.0
Max
350
350
175
125
225
250
300
400
6.0
6.2
5.3
5.5
3.2
3.1
3.5
3.4
1.0
10
10
55
55
+ 0.3
– 0.7
– 0.7
(3)
Unit
MHz
MHz
MHz
mV
mA
Unit
MPC9443 REV. 5 SEPTEMBER 19, 2008
µA
mV
Ω
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ps
ps
ns
V
V
V
V
V
%
%
V
(1)
LVCMOS
LVCMOS
LVPECL
LVPECL
V
I
I
All V
FSELx = 0
FSELx = 1
LVPECL
LVPECL
0.8 to 2.0 V
DC
0.55 to 2.4 V
OH
OL
IN
REF
= 15 mA
= GND or V
= –15 mA
CC
Condition
Condition
= 50%
Pins
(3)
CMR
CMR
(3)
IN
range
= V
range
CC