MC100ES6111FA IDT, Integrated Device Technology Inc, MC100ES6111FA Datasheet - Page 2

• Manufacturer Part Number: MC100ES6111FA
• Description: IC FANOUT BUFFER LV 3GHZ 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 100ESr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MC100ES6111FA

• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: Yes/Yes
• Input: ECL, HSTL, PECL
• Output: ECL, PECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC100ES6111 Data Sheet
MPC100ES6111 REVISION 6 OCTOBER 1, 2009
CLK_SEL
CLKA
CLKA
CLKB
CLKB
Table 2. Function Table
Table 1. Pin Configuration
CLKA, CLKA
CLKB, CLKB
CLK_SEL
Q[0–9], Q[0–9]
V
V
V
1. In ECL mode (negative power supply mode), V
Figure 1. MC100ES6111 Logic Diagram
EE
CC
BB
power supply mode), V
referenced to the most positive supply (V
(1)
CLK_SEL
V
V
Control
CC
CC
Pin
0
1
Input
Input
Input
Output
Supply
Supply
Output
EE
is connected to GND (0 V) and V
Default
I/O
0
CC
V
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
BB
).
CLKA, CLKA input pair is active. CLKA can be
driven by ECL or PECL compatible signals.
ECL/PECL
HSTL/PECL
ECL/PECL
ECL/PECL
DC
EE
is either –3.3 V or –2.5 V and V
Type
V
V
Q2
Q2
Q1
Q1
Q0
Q0
CC
CC
CC
is either +3.3 V or +2.5 V. In both modes, the input and output levels are
Differential reference clock signal input
Alternative differential reference clock signal input
Active clock input select
Differential clock outputs
Negative power supply
Positive power supply. All V
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL or PECL operation
2
0
Figure 2. 32-Lead Package Pinout (Top View)
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER
25
26
27
28
29
30
31
32
24
1
23
2
CC
MC100ES6111
22
3
is connected to GND (0 V). In PECL mode (positive
21
4
CLKB, CLKB input pair is active. CLKB can be
driven by HSTL or PECL compatible signals.
CC
20
5
Function
pins must be connected to the positive
19
6
18
7
©2009 Integrated Device Technology, Inc.
17
8
1
16
15
14
13
12
11
10
9
V
Q7
Q7
Q8
Q8
Q9
Q9
V
CC
CC