ICS889834AKLF IDT, Integrated Device Technology Inc, ICS889834AKLF Datasheet - Page 7

• Manufacturer Part Number: ICS889834AKLF
• Description: IC CLOCK MULT HS 2-4 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS889834AKLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: No/Yes
• Input: LVCMOS, LVTTL
• Output: ECL, LVPECL
• Frequency - Max: 1GHz
• Voltage - Supply: 2.375 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 1GHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: >1000MHz
• Output Logic Level: ECL/LVPECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/3.3V
• Operating Supply Voltage (max): -3.63/3.63V
• Package Type: VFQFN
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 889834AKLF

T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
889834AK
R
I
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
NPUTS
ERMINATION FOR
ECOMMENDATIONS FOR
RTT =
:
F
((V
IGURE
FOUT
OH
ONTROL
+ V
Integrated
Circuit
Systems, Inc.
2A. LVPECL O
OL
) / (V
resistor can be used.
P
1
INS
3.3V LVPECL O
CC
:
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
U
NUSED
Z
o
50Ω
UTPUT
I
NPUT AND
A
T
RTT
ERMINATION
50Ω
www.icst.com/products/hiperclocks.html
UTPUTS
LVCMOS/LVTTL-
PPLICATION
PRELIMINARY
V
CC
FIN
- 2V
O
UTPUT
P
7
INS
I
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
O
LVPECL O
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
UTPUTS
TO
FOUT
F
-LVPECL/ECL C
IGURE
:
UTPUT
2B. LVPECL O
Z
Z
o
o
= 50Ω
= 50Ω
125Ω
84Ω
UTPUT
L
LOCK
OW
3.3V
ICS889834
125Ω
84Ω
T
S
ERMINATION
M
KEW
REV. A MARCH 20, 2006
ULTIPLEXER
FIN
, 2-
TO
-4