ICS83940DY-01LFT IDT, Integrated Device Technology Inc, ICS83940DY-01LFT Datasheet
ICS83940DY-01LFT
Specifications of ICS83940DY-01LFT
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ICS83940DY-01LFT Summary of contents
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G D ENERAL ESCRIPTION The ICS83940- low skew, 1-to-18 LVPECL-to- LVCMOS/LVTTL Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels. The single ended clock input accepts ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Input Current Storage Temperature, T -40°C to 125°C STG T 4A ...
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T 4C ABLE HARACTERISTICS ...
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T 5B 3.3V ± 5%, V ABLE HARACTERISTICS ...
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T 5C ABLE HARACTERISTICS ...
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P ARAMETER 1.65V±5% V DD, V DDO LVCMOS GND -1.65V±5% 3. UTPUT OAD EST IRCUIT 1.25V±5% V DD, V DDO LVCMOS GND -1.25V±5% 2. UTPUT OAD EST IRCUIT PART 1 ...
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Clock t Outputs UTPUT ISE ALL IME V DDO 2 LVCMOS_CLK nPCLK PCLK V DDO 2 Q0:Q17 ROPAGATION ELAY 83940DY-01 LVPECL- -LVCMOS / LVTTL F TO 80% Q0:Q17 20% ...
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IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show CMR interface examples for the PCLK/nPCLK input driven ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the ...
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ACKAGE UTLINE UFFIX FOR EAD ABLE ACKAGE ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...