ICS85310AYI-21LN IDT, Integrated Device Technology Inc, ICS85310AYI-21LN Datasheet - Page 7

• Manufacturer Part Number: ICS85310AYI-21LN
• Description: IC FANOUT BUFFER 1-5 DUAL 32LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS85310AYI-21LN

• Number Of Circuits: 2
• Ratio - Input:output: 1:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: ECL, LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 2.375 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85310AYI-21LN

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
85310AYI-21
RTT =
ERMINATION FOR
IRING THE
((V
F
FOUT
IGURE
OH
+ V
D
OL
2A. LVPECL O
IFFERENTIAL
) / (V
1
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
I
F
NPUT TO
Z
IGURE
o
50Ω
UTPUT
Single Ended Clock Input
D
1. S
IFFERENTIAL
A
T
RTT
A
ERMINATION
UTPUTS
50Ω
PPLICATION
CCEPT
INGLE
V
CC
C1
0.1u
FIN
- 2V
E
S
V_REF
NDED
INGLE
CC
www.idt.com
-
/2 is
TO
S
IGNAL
-2.5V/3.3V ECL/LVPECL F
E
7
NDED
I
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
1K
R1
1K
R2
D
VCC
RIVING
L
FOUT
EVELS
nCLKx
F
CLKx
IGURE
D
IFFERENTIAL
2B. LVPECL O
Z
Z
o
o
= 50Ω
= 50Ω
L
I
NPUT
OW
CC
125Ω
84Ω
= 3.3V, V_REF should be 1.25V
ICS85310I-21
S
KEW
UTPUT
3.3V
, D
ANOUT
125Ω
84Ω
T
ERMINATION
REV. E AUGUST 13, 2010
UAL
FIN
, 1-
B
UFFER
TO
-5