NB4L16MMNG ON Semiconductor, NB4L16MMNG Datasheet
NB4L16MMNG
Specifications of NB4L16MMNG
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NB4L16MMNG Summary of contents
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NB4L16M 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer/ Translator with Internal Termination Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL and produce 400 mV CML output. ...
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Table 1. PIN DESCRIPTION Pin Name LVPECL, CML, HSTL, LVCMOS, LVDS, LVTTL Input 3 D LVPECL, CML, HSTL, LVCMOS, LVDS, LVTTL Input CML Output 11 ...
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Table 2. ATTRIBUTES Input Default State Resistors ESD Protection Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter ...
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Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS Symbol Characteristic I Power Supply Current (Inputs and Outputs Open Output HIGH Voltage (Note Output LOW Voltage (Note 4) OL DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 15 and ...
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Table 5. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude (@V OUTPP (Figures 3 and 4) f Maximum Operating Data Rate DATA t , Propagation Delay to Output Differential @ 0.5 GHz PLH t (Figure 6) PHL t Duty ...
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TYPICAL OPERATING CHARACTERISTICS 450 400 350 300 +85°C 250 +25°C 200 150 100 2.5 3 3.5 4 INPUT CLOCK FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (V vs. Input Clock Frequency (f Temperature at 3.3 V ...
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Device DDJ = 1.5 ps TIME (80 ps/div) Figure 7. Typical Output Waveform at 2.488 Gb/s 23 with PRBS 2 − mV; Input Signal INPP DDJ = 12 ps) Device DDJ = 1.5 ps TIME (72 ps/div) ...
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Figure 13. AC Reference Measurement Q Driver Device Q Figure 14. Typical Termination for Output Driver and Device Evaluation Figure 15. Differential Input Driven Single−Ended thmax ...
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Table 6. INTERFACING OPTIONS INTERFACING OPTIONS CML Connect V TD LVDS Connect V TD AC−COUPLED Bias V and V TD RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An External Voltage ( 1.5 V for LVTTL and ...
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All NB4L16M inputs can accept LVPECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing and the maximum input swing of 2500 mV. Within these ...
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... Driver V EE Figure 23. LVCMOS/LVTTL to CML Receiver Interface ORDERING INFORMATION Device NB4L16MMN NB4L16MMNG NB4L16MMNR2 NB4L16MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ Figure 22. LVDS to CML Receiver Interface ...
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... E2 e 3.25 0.128 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6,362,644. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...