NB6HQ14MMNHTBG ON Semiconductor, NB6HQ14MMNHTBG Datasheet - Page 3

• Manufacturer Part Number: NB6HQ14MMNHTBG
• Description: IC BUFFER FANOUT 1:4 CML 16-QFN
• Manufacturer: ON Semiconductor
• Series: ECLinPS MAX™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of NB6HQ14MMNHTBG

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: CML
• Frequency - Max: 5GHz
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Frequency-max: 5GHz
• Logic Family: NB6HQ14
• Logic Type: CML Fanout Buffer
• Supply Voltage (max): 2.625 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Rate: 10 Gbps
• Minimum Operating Temperature: - 40 C
• Output Current: +/- 40 mA
• Output Voltage: - 0.5 to + 3.5 V
• Propagation Delay Time: 220 ps
• Supply Current: 75 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
2. All VCC, VCCO and GND pins must be externally connected to a power supply for proper operation.
Table 2. PIN DESCRIPTION
Pin
10
12
13
14
15
16
11
VREFAC
1
2
3
4
5
6
7
8
9
−
is applied on IN / IN input, then, the device will be susceptible to self−oscillation.
VT
IN
IN
VREFAC
EQEN
VCCO
Name
GND
VCC
Figure 2. QFN−16 Pinout (Top View)
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
EP
VT
IN
IN
1
2
3
4
EQEN Q3
GND Q0
16
5
LVPECL, CML,
LVPECL, CML,
LVCMOS Input
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
LVDS Input
LVDS Input
NB6HQ14M
15
6
I/O
−
−
−
−
Q0
14
Q3 V
7
V
13
CCO
8
CC
Non−inverted Differential Input. Note 1.
Internal 100 W Center−tapped Termination Pin for IN / IN
Output Voltage Reference for Capacitor−Coupled Inputs, only
Inverted Differential Input. Note 1.
Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor)
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
1.8 V or 2.5 V Positive Supply Voltage for the Qn / Qn CML Outputs
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
2.5 V Positive Supply Voltage for the core
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
Negative Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally con-
nected to GND on the PC board.
Exposed Pad (EP)
12
10
11
9
Q1
Q1
Q2
Q2
http://onsemi.com
3
Table 1. EQUALIZER ENABLE FUNCTION
EQEN
0
1
Description
IN / IN Inputs By−pass the Equalizer section
Inputs flow through the Equalizer
Function
CC
CC
CC
CC
.
.
.
.
CC
CC
CC
CC
.
.
.
.