100LVEL11MX Fairchild Semiconductor, 100LVEL11MX Datasheet

100LVEL11MX

Manufacturer Part Number

100LVEL11MX

Description

IC FANOUT BUFFER 3.3V ECL 8SOIC

Manufacturer

Fairchild Semiconductor

Series

100LVELr

Type

Fanout Buffer (Distribution)r

Datasheet

1.100LVEL11M.pdf (6 pages)

Specifications of 100LVEL11MX

Number Of Circuits

Ratio - Input:output

1:2

Differential - Input:output

Yes/Yes

Input

ECL

Output

ECL

Voltage - Supply

3 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

8-SOIC (3.9mm Width)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Frequency-max

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100LVEL11M

100LVEL11M8

(Preliminary)

100LVEL11

3.3V ECL 1:2 Differential Fanout Buffer

General Description

The 100LVEL11 is a low voltage 1:2 differential fanout

buffer. One differential input signal is fanned out to two

identical differential outputs. By supplying a constant refer-

ence level to one input pin a single ended input condition is

created.

With inputs Open or both inputs at V

outputs default LOW and Q outputs default HIGH.

The 100 series is temperature compensated.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Order Number

D, D

, Q

Pin Name

, Q

Package

Number

MA08D

M08A

Top View

Top Mark

Product

ECL Data Outputs

ECL Data Inputs

Positive Supply

Negative Supply

KVL11

Code

KV11

Description

, the differential Q

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide

DS500775

Features

Logic Diagram

Typical propagation delay of 330 ps

Typical I

Typical skew of 5 ps between outputs

Internal pull-down resistors on D

Fairchild MSOP-8 package is a drop-in replacement to

ON TSSOP-8

Meets or exceeds JEDEC specification EIA/JESD78 IC

latch-up tests

Moisture Sensitivity Level 1

ESD Performance:

Human Body Model

Machine Model

Package Description

of 24 mA

200V

2000V

January 2003

Revised January 2003

www.fairchildsemi.com

Related parts for 100LVEL11MX

100LVEL11MX Summary of contents

Page 1

... D, D ECL Data Inputs V Positive Supply CC V Negative Supply EE © 2003 Fairchild Semiconductor Corporation Features Typical propagation delay of 330 ps Typical Typical skew between outputs Internal pull-down resistors on D Fairchild MSOP-8 package is a drop-in replacement to ON TSSOP-8 Meets or exceeds JEDEC specification EIA/JESD78 IC latch-up tests ...

Page 2

Absolute Maximum Ratings PECL Supply Voltage ( NECL Supply Voltage ( PECL DC Input Voltage ( NECL DC Input Voltage ( ...

Page 3

LVNECL DC Electrical Characteristics Symbol Parameter I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single Ended Input LOW Voltage (Single Ended ...

Page 4

Switching Waveforms FIGURE 1. Differential to Differential Propagation Delay FIGURE 2. Differential Output Edge Rates www.fairchildsemi.com 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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