ICS85354AKLFT IDT, Integrated Device Technology Inc, ICS85354AKLFT Datasheet - Page 2

• Manufacturer Part Number: ICS85354AKLFT
• Description: IC MUX DUAL 2:1 1:2 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Multiplexerr

Specifications of ICS85354AKLFT

• Number Of Circuits: 2
• Ratio - Input:output: 2:1, 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 3.2GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 3.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85354AKLFT

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Tables
Table 3A. Control Input Function Table, (Bank A)
IDT™ / ICS™ LVPECL/ECL MULTIPLEXER
Symbol
R
R
ICS85354
DUAL 2:1 AND 1:2, DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
VCC/2
PULLDOWN
Number
Control Input
15, 16
CLK_SELA
1, 2
3, 4
10
11
12
13
14
5
6
7
8
9
0
1
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistor
CLK_SELB
CLK_SELA
QB0/QB0
QB1/QB1
Bank A
CLKA1
CLKA1
CLKA0
CLKA0
QA/QA
Name
CLKB
CLKB
Outputs
QA/QA
Selects CLKA0/CLKA0
Selects CLKA1/CLKA1
V
V
CC
EE
Output
Output
Output
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pullup/
Pullup/
Test Conditions
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. V
Clock select pin for QBx outputs. When HIGH, selects QB1/QB1 outputs.
When LOW, selects QB0/QB0 outputs. LVCMOS/LVTTL interface levels.
Negative supply pin.
Inverting differential LVPECL clock input. V
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. V
Non-inverting LVPECL/ECL differential clock input.
Positive supply pin.
Clock select pin for QA output. When HIGH, selects QA output. When LOW,
selects QA output. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL/ECL interface levels.
2
Table 3B. Control Input Function Table, (Bank B)
Control Input
CLK_SELB
0
1
Minimum
Outputs
QB0/QB0
Follows CLKB input
Low
ICS85354AK REV. C NOVEMBER 04, 2008
Bank B
Typical
CC
CC
CC
37.5
37.5
/2 default when left floating.
/2 default when left floating.
/2 default when left floating.
Maximum
QB1/QB1
Low
Follows CLKB input
Units
k
k
Ω
Ω