DS0026CN National Semiconductor, DS0026CN Datasheet - Page 8

• Manufacturer Part Number: DS0026CN
• Description: IC CLOCK DRIVER DUAL 5MHZ 8-DIP
• Manufacturer: National Semiconductor
• Type: Fanout Buffer (Distribution)r

Specifications of DS0026CN

• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Input: TTL
• Output: MOS
• Frequency - Max: 10MHz
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Frequency-max: 10MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply: -
• Other names: *DS0026CN; DS0026

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Lastly, the clock lines must be considered as noise genera-
tors.
coupling capacitor, C
by a 7404. A parasitic lumped line inductance, L, is also
shown. Let us assume, for the sake of argument, that C
pF and that the rise time of the clock is high enough to com-
pletely isolate the clock transient from the 7404 because of
the inductance, L.
With a clock transition of 20V the magnitude of the voltage
generated across C
This has been a hypothetical example to emphasize that with
20V low rise/fall time transitions, parasitic elements can not
Figure 5
shows a clock coupled through a parasitic
FIGURE 5. Clock Coupling
L
C
is:
, to eight data input lines being driven
5853 Version 6 Revision 3
585320
C
is 1
Print Date/Time: 2010/07/13 22:49:07
8
be neglected. In this example, 1 pF of parasitic capacitance
could cause system malfunction, because a 7404 without a
pull up resistor has typically only 0.3V of noise margin in the
“1” state at 25°C. Of course it is stretching things to assume
that the inductance, L, completely isolates the clock transient
from the 7404. However, it does point out the need to mini-
mize inductance in input/output as well as clock lines.
The output is current, so it is more meaningful to examine the
current that is coupled through a 1 pF parasitic capacitance.
The current would be:
This exceeds the total output current swing so it is obviously
significant.
Clock coupling to inputs and outputs can be minimized by us-
ing multilayer printed circuit boards, as mentioned previously,
physically isolating clock lines and/or running clock lines at
right angles to input/output lines. All of these techniques tend
to minimize parasitic coupling capacitance from the clocks to
the signals in question.
In considering clock coupling it is also important to have a
detailed knowledge of the functional characteristics of the de-
vice being used. As an example, for the MM5262, coupling
noise from the φ2 clock to the address lines is of no particular
consequence. On the other hand the address inputs will be
sensitive to noise coupled from φ1 clock.