NB100EP223FA ON Semiconductor, NB100EP223FA Datasheet - Page 5

• Manufacturer Part Number: NB100EP223FA
• Description: IC DRIVER CLOCK 1:22 3.3V 64LQFP
• Manufacturer: ON Semiconductor
• Series: 100EPr
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of NB100EP223FA

• Number Of Circuits: 1
• Ratio - Input:output: 2:22
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVDS, LVPECL
• Output: HSTL
• Frequency - Max: 500MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LSQFP Exposed Pad
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: NB100EP223FAOS

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
4. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to ground
5. Skew is measured between outputs under identical transitions and conditions on any one device.
6. Device−to−Device skew for identical transitions at identical V
7. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
8. V
Table 8. AC CHARACTERISTICS
V
t
t
t
t
V
t
t
t
PLH
PHL
skew
JITTER
S
H
r
Symbol
/t
Opp
PP
(See Figure 6).
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (See Figure 7).
f
PP
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
is the differential input voltage swing required to maintain AC characteristics including t
Figure 3. Output Frequency (F
Differential Output Voltage
(Figure 3)
Propagation Delay (Differential)
Within−Device Skew (Note 5)
Device−to−Device Skew (Note 6)
Random Clock Jitter (Figure 3) (RMS)
Input Swing (Differential Mode)
(Note 8) (Figure 4)
OE Set Up Time (Note 7)
OE Hold Time
Output Rise/Fall Time (20%−80%)
Characteristic
900
800
700
600
500
400
300
200
0.5
V
LVPECL_CLK to Q
CC
HSTL_CLK to Q
LVPECL, HSTL
= 3.0 V to 3.6 V; V
f
out
OUT
< 500 MHz
0.6
) versus Output Voltage (V
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FREQUENCY (GHz)
RMS JITTER (ps)
0.7
Min
600
700
800
150
300
1.0
0.5
CCO
CC
Q AMP (mV)
levels.
= 1.6 V to 2.0 V; GND = 0 V (Note 4)
5
0°C
Typ
750
900
900
100
800
450
0.5
25
0.8
1000
1100
1200
Max
250
700
50
2
OPP
0.9
Min
600
750
850
150
275
) and Random Clock Jitter (t
1.0
0.5
25°C
Typ
750
900
950
200
800
450
0.5
30
PD
1.0
and device−to−device skew.
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
1200
1200
1100
Max
450
700
65
2
Min
600
800
850
150
350
1.0
0.5
85°C
1000
1050
Typ
700
250
800
500
0.5
50
JITTER
1300
1350
1200
Max
115
450
750
2
)
Unit
mV
mV
ps
ps
ps
ps
ps
ns
ns
ps