MC100E210FN ON Semiconductor, MC100E210FN Datasheet

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MC100E210FN

Manufacturer Part Number
MC100E210FN
Description
IC BUFFER DUAL 1:4/5 ECL 28-PLCC
Manufacturer
ON Semiconductor
Series
100Er
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of MC100E210FN

Number Of Circuits
2
Ratio - Input:output
1:4, 1:5
Differential - Input:output
Yes/Yes
Input
ECL, PECL
Output
ECL, PECL
Frequency - Max
700MHz
Voltage - Supply
4.2 V ~ 5.7 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
700MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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MC100E210FN
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Quantity:
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MC100E210
5V ECL Dual 1:4, 1:5
Differential Fanout Buffer
fanout buffer designed with clock distribution in mind. The device
features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The
device features fully differential clock paths to minimize both device and
system skew. The dual buffer allows for the fanout of two signals through
a single chip, thus reducing the skew between the two fundamental
signals from a part−to−part skew down to an output−to−output skew. This
capability reduces the skew by a factor of 4 as compared to using two
LVE111’s to accomplish the same task.
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10−20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
Application Note AN1406/D.
device only. For single-ended input conditions, the unused differential
input is connected to V
rebias AC coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, V
October, 2003 − Rev. 2
The MC100E210 is a low voltage, low skew dual differential ECL
The lowest TPD delay time results from terminating only one output
For more information on using PECL, designers should refer to
The V
NECL Mode Operating Range: V
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
Dual Differential Fanout Buffers
200 ps Part−to−Part Skew
50 ps Typical Output−to−Output Skew
Low Voltage ECL/PECL Compatible
The 100 Series Contains Temperature Compensation
28−lead PLCC Packaging
PECL Mode Operating Range: V
Internal Input 75 KW Pulldown Resistors
Q Output will Default LOW with Inputs Open or at V
ESD Protection: Human Body Model; >2 KV,
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V−0 @ 0.125 in,
Transistor Count = 179 devices
Semiconductor Components Industries, LLC, 2003
BB
BB
pin, an internally generated voltage supply, is available to this
should be left open.
Machine Model; >200 V
BB
as a switching reference voltage. V
CC
CC
= 0 V with V
= 4.2 V to 5.7 V with V
EE
BB
= −4.2 V to −5.7 V
and V
EE
BB
CC
may also
1
EE
via a
= 0 V
*For additional information, see Application Note
†For information on tape and reel specifications,
MC100E210FN
MC100E210FNR2
AND8002/D
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Device
FN SUFFIX
ORDERING INFORMATION
CASE 776
PLCC−28
A
WL = Wafer Lot
YY = Year
WW = Work Week
http://onsemi.com
= Assembly Location
PLCC−28 500 Tape & Reel
Package
PLCC−28
Publication Order Number:
MC100E210FN
MARKING
DIAGRAM
AWLYYWW
37 Units / Rail
MC100E210/D
Shipping
1 28

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MC100E210FN Summary of contents

Page 1

... ORDERING INFORMATION Device Package Shipping MC100E210FN PLCC−28 37 Units / Rail MC100E210FNR2 PLCC−28 500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MC100E210/D † ...

Page 2

LOGIC DIAGRAM AND PINOUT ASSIGNMENT Qa0 Qa0 Qa1 V Qa1 Qa2 Qa2 CCO CLKa 28−Lead PLCC (Top View) 2 CLKa 3 CLKb CLKb 4 5 ...

Page 3

PECL DC CHARACTERISTICS V CCx Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 4

AC CHARACTERISTICS CCx Symbol Characteristic f Maximum Toggle Frequency MAX t Propagation Delay to Output PLH t IN (differential) (Note 9) PHL IN (single−ended) (Note 10) t Within−Device Skew skew Qa to Qa, ...

Page 5

Driver Device Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard V AN1405 − ECL Clock Distribution ...

Page 6

− 0.010 (0.250) NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY ...

Page 7

Notes MC100E210 http://onsemi.com 7 ...

Page 8

... Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com MC100E210 N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 ON Semiconductor Website: http://onsemi ...

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