CY25562SXC Cypress Semiconductor Corp, CY25562SXC Datasheet
CY25562SXC
Specifications of CY25562SXC
CY25562SXC
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CY25562SXC Summary of contents
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... Center Spread Modulation ■ Low Cycle-to-cycle Jitter ■ 8-pin SOIC Package ■ Logic Block Diagram Cypress Semiconductor Corporation Document Number: 38-07392 Rev. *D Spread Spectrum Clock Generator Applications High resolution VGA controllers ■ LCD panels and monitors ■ Workstations and servers ■ ...
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Pinout Pin Description Pin # Pin Name Type 1 Xin/CLK I Clock or crystal connection input. Refer to 2 VDD P Positive power supply 3 GND P Power supply ground 4 SSCLK O SSCG modulated clock output 5 SSCC I ...
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Table 1. Frequency and Spread Percentage Selection (Center Spread – ...
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SSCG SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle-to-cycle. CY25562 takes a narrow band digital reference clock in the range 200 MHz ...
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Part Number Application Schematic 200 MHz Reference Clock VDD The schematic in Figure 4 demonstrates how CY25562 is configured in a typical application. This application is using a 200 MHz reference clock connected to pin 1. Because an external reference ...
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... CJ3 Ordering Information Part Number CY25562SXC 8-pin SOIC, Pb-free CY25562SXCT 8-pin SOIC – tape and reel, Pb-free Notes 1. Operation at any absolute maximum rating is not implied. 2. Single power supply: The voltage on any input or I/O pin cannot exceed the power pine during power-up. ...
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Package Drawing and Dimensions Document Number: 38-07392 Rev. *D Figure 5. 8 Lead (150 Mil) SOIC-SO8 CY25562 51-85066 *D Page [+] Feedback ...
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... New Data Sheet RGL Corrected the values in the Absolute Maximum Ratings to match the device. RBI Added power up requirements to maximum ratings information. PYG/KVM/ Replaced CY25562SC w/ CY25562SXC, CY255652SCT w/ CY25562SXCT. AESA Package changed from S8 to SZ8. Updated template. CXQ Updated package diagram. Revised March 04, 2011 ...