CY24293ZXC Cypress Semiconductor Corp, CY24293ZXC Datasheet - Page 7

• Manufacturer Part Number: CY24293ZXC
• Description: IC CLK BUFFER 2PR 3.3V 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY24293ZXC

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Clock, Crystal
• Output: HCSL, LVDS
• Ratio - Input:output: 1:3
• Differential - Input:output: No/Yes
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Minimum Input Frequency: 25 MHz
• Output Frequency Range: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

,
AC Electrical Characteristics
Unless otherwise stated: VDD = 3.3V ±0.3V, ambient temperature = -40 °C to +85 °C Industrial, 0°C to +70°C Commercial, Outputs
HCSL terminated.
Test and Measurement Setup
Document Number: 001-46117 Rev. *C
F
F
F
T
SP
T
T
T
T
T
T
DT
DT
T
V
V
Notes
Parameter
4. Measured with Cload = 4 pF max. (scope probe + trace load)
5. Measurement taken from a differential waveform.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
8. Refers to the difference between the PCIEP rising edge V
OEH
OEL
OSKEW
IN
OUT
ERR
CCJ
DC
LOCK
R
F
CROSS
Xdelta
MOD
R
F
[3]
Input clock frequency (crystal or
external clock)
Output frequency
Frequency synthesis error
Cycle-to-cycle jitter
Spread modulation frequency
Output clock duty cycle
Output enable time
Output disable time
Clock stabilization from power up
Output rise time
Output fall time
Rise time variation
Fall time variation
Output skew
Absolute crossing point voltage
Variation of V
edges
[6,8]
Description
[6]
CROSS
Figure 5. Test Load Configuration for Differential Output Signals
[4,5]
[4,5]
[4,5]
[4,5]
[4]
over all clock
PCIEN
PCIEP
[4,6]
475
Ohm
[6,7]
CROSS
33 Ohm
33 Ohm
HCSL Termination
LVDS Termination
OE going high to differential outputs
becoming valid
OE going low to differential outputs
becoming invalid
Measured from 90% of the applied power
supply level
Measured from 0.175V to 0.525V
Measured from 0.525V to 0.175V
For a given frequency, Max(T
For a given frequency, Max(T
Measured at V
average value and the PCIEN rising edge V
CROSS
Condition
point
CLoad
CLoad
R
F
) - Min (T
) - Min (T
CROSS
50 Ohm
50 Ohm
F
R
average value.
)
)
0.25
Min
130
130
45
–
–
–
–
–
–
–
–
–
–
–
–
–
0.35
Typ
25
32
50
–
–
0
–
–
–
1
–
–
–
–
–
–
CY24293
Max
0.55
200
100
200
200
700
700
125
125
140
75
55
50
–
–
–
2
Page 7 of 10
MHz
MHz
MHz
Unit
ppm
kHz
mV
ms
ps
ns
ns
ps
ps
ps
ps
ps
%
V
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