CY23EP05SXC-1 Cypress Semiconductor Corp, CY23EP05SXC-1 Datasheet - Page 2

• Manufacturer Part Number: CY23EP05SXC-1
• Description: IC CLK ZDB 5OUT 220MHZ 8SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY23EP05SXC-1

• Number Of Circuits: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Pll: Yes
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:5
• Differential - Input:output: No/No
• Frequency - Max: 133MHz, 167MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 220MHz
• Maximum Input Frequency: 220 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 220 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Number Of Elements: 1
• Supply Current: 45mA
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 220MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SOIC
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Pin Count: 8
• Clock Ic Type: Clock Buffer
• Frequency: 220MHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 1
• Supply Voltage Range: 2.3V To 2.7V, 3V To 3.6V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-07759 Rev. *B
Pin Description
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Pin
1
2
3
4
5
6
7
8
REF
CLK2
CLK1
GND
CLK3
V
CLK4
CLKOUT
DD
[1]
[2]
[2]
[2]
[2]
Signal
[2,3]
Input reference frequency
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V or 2.5V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
titled “CY2305 and CY2309 as PCI and SDRAM Buffers”.
Description
CY23EP05
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