LMX2541SQE3740E/NOPB National Semiconductor, LMX2541SQE3740E/NOPB Datasheet - Page 10

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LMX2541SQE3740E/NOPB

Manufacturer Part Number
LMX2541SQE3740E/NOPB
Description
IC PLL FREQ SYNTH W/VCO 36LLP
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Clock/Frequency Synthesizer (RF)r
Datasheet

Specifications of LMX2541SQE3740E/NOPB

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
No/No
Frequency - Max
4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-LLP
Frequency-max
4GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMX2541SQE3740ETR

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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
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Quantity:
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Symbol
t
t
Note 5: The LMX2541 RFout power level is programmable with the program words of VCOGAIN, OUTTERM, and DIVGAIN. Changing these words can change
the output power of the VCO as well as the current consumption of the output buffer. For the purpose of consistency in electrical specifications, "Default Power
Mode" is defined to be the settings of VCOGAIN = OUTTERM = DIVGAIN = 12.
Note 6: The measurement of the output power is sensitive to the test circuit. All the numbers in the electrical specifications and typical performance curves were
obtained from a characterization setup that accomodated temperature testing and changing of parts. In a more optimized setup the measured RF output power
is typically on the order of 1.5 to 2.4 dB higher.
Note 7: Not tested in production. Guaranteed by characterization. OSCin is tested only to 400 MHz.
Note 8: Consult the applications section for more details on these parameters.
Note 9: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the device stay in lock. The action of programming the R0 register, even to the same value, activates a
frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum allowable
drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the device was initially
programmed at, the temperature can never drift outside the frequency range of -40°C
Note 10: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The phase noise is measured
with AC_TEMP_COMP = 5 and the device is reloaded at each test frequency. The typical performance characteristics section shows how the VCO phase noise
varies over temperature and frequency.
Note 11: See Typical Performance Characteristics for more information.
Note 12: The duty cycle error (DE) and second harmonic (HS) are theoretically related by the equation HS = 10·log| 2
cycle theoretically has a second harmonic of -20 dBc.
I
t
V
t
V
CWH
EWH
V
V
Leak
t
t
t
CWL
CES
I
I
CE
CS
CH
IH
IL
OH
OL
IH
IL
Enable to Clock Set Up Time
Data to Clock Set Up Time
High-Level Output Voltage
Clock to Enable Low Time
Low-Level Output Voltage
Enable Pulse Width High
High-Level Input Voltage
High-Level Input Current
Low-Level Input Voltage
Data to Clock Hold Time
Low-Level Input Current
Clock Pulse Width High
Clock Pulse Width Low
Leakage Current
Parameter
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout,RFoutEN)
MICROWIRE Timing
Ftest/LD and FLout Pins Only
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
V
V
IH
IL
I
I
OL
Conditions
OH
= 1.75, XO = 0
= 0 V , XO = 0
10
= -500 µA
= 500 µA
T
A
85°C without violating specifications.
π
·DE | - 6 dB. A square wave with 3% duty
Min
1.6
2.0
25
25
20
25
25
25
25
-5
-5
-5
Typ
0.0
Max
Vcc
0.4
0.4
5
5
5
Units
µA
µA
µA
ns
ns
ns
ns
ns
ns
ns
V
V
V
V

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