CY223931FXI Cypress Semiconductor Corp, CY223931FXI Datasheet
CY223931FXI
Specifications of CY223931FXI
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CY223931FXI Summary of contents
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... Digital VCXO ■ High frequency LVPECL output (CY22394 only) ■ 3.3/2.5V outputs (CY22395 only) ■ NiPdAu lead finish (CY223931) Cypress Semiconductor Corporation Document #: 38-07186 Rev. *F CY22393, CY223931, CY22394, CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator Benefits ■ Generates up to three unique frequencies six outputs from an external source. ■ ...
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Selector Guide Part Number Outputs Input Frequency Range CY22393_C 6 CMOS 8 MHz–30 MHz (external crystal) 1 MHz–166 MHz (reference clock) CY22393_I 6 CMOS 8 MHz–30 MHz (external crystal) 1 MHz–166 MHz (reference clock) CY223931_I 6 CMOS 8 MHz–30 MHz ...
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Logic Block Diagram - CY22394 XTALIN OSC. XTALOUT CONFIGURATION FLASH SHUTDOWN/OE SCLK SDAT S2/SUSPEND Logic Block Diagram - CY22395 XTALIN OSC. XTALOUT CONFIGURATION FLASH SHUTDOWN/OE SCLK SDAT S2/SUSPEND LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD Document #: 38-07186 Rev. *F ...
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Pinouts Figure 1. Pin diagram - 16-Pin TSSOP CY22393/CY223931/CY22394/CY22394 CY22393 CY223931 CY22393 UTDOWN / /SU SPEND AGND XTALIN SC LK (S1) 12 XTALOUT 5 ...
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Operation The CY22393, CY22394, and CY22395 are a family of parts designed as upgrades to the existing CY22392 device. These parts have similar performance to the CY22392, but provide advanced features to meet the needs of more demanding applications. The ...
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LV PECL Clock referenced to CLKE, bypassing both the cross point switch and 7-bit post divider. CLKE’s output originates from PLL1 and goes through a post divider that may be programmed to /2, /3, or /4. For the CY22394, ...
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Clk*_FS[2:0] Each of the four main output clocks (CLKA–CLKD) has a three-bit code that determines the clock sources for the output divider. The available clock sources are: Reference, PLL1, PLL2, and PLL3. Each PLL provides both positive and negative phased ...
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OscDrv[1:0] These bits control the crystal oscillator gain setting. These must always be set according to Table 5. The parameters are the Crystal Frequency, Internal Crystal Parasitic Resistance (available from the manufacturer), and the OscCap setting during crystal start up, ...
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Addr S2 (1, 49H 011 4AH 4BH DivSel PLL1_En 4CH 100 4DH 4EH DivSel PLL1_En 4FH 101 50H 51H DivSel PLL1_En 52H 110 53H 54H DivSel PLL1_En 55H 111 56H 57H DivSel PLL1_En Serial Bus Programming Protocol and ...
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Write Operations Writing Individual Bytes A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (ack = 0/LOW). The next eight ...
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Bit Write 1 Bit Slave SDAT ACK R Multiple 7-bit 8-bit Contiguous Device Register Registers Address Address (XXH) Start Signal 1 Bit 1 Bit Read SDAT Slave ACK R Current 7-bit 8-bit Device Register Address ...
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Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data) SDAT + START DA6 DA5 DA0 R/W + SCLK Serial Programming Interface Timing Specifications Parameter Description f Frequency of SCLK SCLK Start mode time from SDA LOW to SCL ...
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Absolute Maximum Conditions Supply Voltage................................................–0.5V to +7.0V DC Input Voltage ........................... –0. (AV Storage Temperature .................................. –65°C to +125°C Junction Temperature .................................................. 125°C Data Retention at Tj=125×C..................................> 10 years Maximum Programming Cycles....................................... 100 Package Power Dissipation ...................................... 350 ...
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Switching Characteristics Parameter Description [4, 6] 1/t Output Frequency 1 [ Output Duty Cycle 2 t Rising Edge Slew Rate 3 t Falling Edge Slew Rate 4 t Output three-state Timing 5 [ Clock Jitter ...
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Switching Waveforms Figure 7. All Outputs, Duty Cycle and Rise and Fall Time OUTPUT ALL TRI-STATE OUTPUTS CLK OUTPUT P– SELECT CPU Document #: 38-07186 Rev. *F CY22393, CY223931, CY22394, CY22395 ...
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Test Circuit AV DD 0.1 μF (L)V DD 0.1 μF Document #: 38-07186 Rev. *F CY22393, CY223931, CY22394, CY22395 Figure 12. Test Circuit CLK out LOAD P+/P- out GND Page [+] Feedback [+] Feedback ...
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... TSSOP - Tape and Reel CY22393FXC 16-pin TSSOP CY22393FXCT 16-pin TSSOP - Tape and Reel CY22393FXI 16-pin TSSOP CY22393FXIT 16-pin TSSOP - Tape and Reel CY223931FXI 16-pin TSSOP with NiPdAu lead finish CY22394ZXC-xxx 16-pin TSSOP CY22394ZXC-xxxT 16-pin TSSOP - Tape and Reel CY22394ZXI-xxx 16-pin TSSOP CY22394ZXI-xxxT ...
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Package Diagram Figure 13. 16-Pin TSSOP 4.40 MM Body Z16.173 1 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document #: 38-07186 Rev. *F CY22393, CY223931, CY22394, CY22395 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. ...
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... Replaced I C references with “2-wire serial interface” 01/09/09 Changed title to include CY223931. Added CY223931 to page 1 features list. Added part number CY223931FXI. Added CY22393_I to the Selector Guide (p.2), and changed the format of the part numbers. Added overbar to SUSPEND in Pin Definitions table 08/10/09 Posting to external web ...