CY7B991-5JI Cypress Semiconductor Corp, CY7B991-5JI Datasheet - Page 4
![IC CLK BUFF SKEW 8OUT 32PLCC](/photos/16/11/161138/plcc32_sml.jpg)
CY7B991-5JI
Manufacturer Part Number
CY7B991-5JI
Description
IC CLK BUFF SKEW 8OUT 32PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet
1.CY7B991-7JXC.pdf
(20 pages)
Specifications of CY7B991-5JI
Number Of Circuits
1
Package / Case
32-PLCC
Pll
Yes
Input
TTL
Output
TTL
Ratio - Input:output
1:4
Differential - Input:output
No/No
Frequency - Max
80MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
80MHz
Output Frequency Range
3.75 MHz to 80 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7B991-5JI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7B991-5JIT
Manufacturer:
PANASONIC
Quantity:
818
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (t
frequency of the device and the level of the FS pin as shown in
Table
Table 2. Frequency Range Select and t
Document Number: 38-07138 Rev. *E
Notes
FS
LOW
MID
HIGH
1. For all tri-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
2. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V.
[2, 3]
holds an unconnected input to VCC/2.
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
2.
f
Min
NOM
15
25
40
(MHz)
Max
30
50
80
t
U
where N =
=
----------------------- -
f
44
26
16
NOM
U
) is determined by the operating
1
×
N
Frequency (MHz) At
Which t
U
Approximate
Calculation
22.7
38.5
62.5
U
= 1.0 ns
[1]
Skew Select Matrix
The skew select matrix contains four independent sections. Each
section has two low skew, high fanout drivers (xQ0, xQ1), and
two corresponding three level function select (xF0, xF1) inputs.
Table 3
as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0t
Table 3. Programmable Skew Configurations
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
1F1, 2F1,
3F1, 4F1
Function Selects
shows the nine possible output functions for each section
1F0, 2F0,
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
3F0, 4F0
Table
1Q0, 1Q1,
2Q0, 2Q1
3). The frequency appearing at the REF and FB
–4t
–3t
–2t
–1t
+1t
+2t
+3t
+4t
0t
U
Logic Block
U
U
U
U
U
U
U
U
U
Output Functions
selected.
Divide by 2 Divide by 2
Divide by 4
3Q0, 3Q1
Diagram). Nominal frequency
–6t
–4t
–2t
+2t
+4t
+6t
0t
U
U
U
U
U
U
U
CY7B991
CY7B992
[1]
4Q0, 4Q1
Page 4 of 20
Inverted
–6t
–4t
–2t
+2t
+4t
+6t
0t
U
U
U
U
U
U
U
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