MB15E03SLPFV1-G-BND-6E1 Fujitsu Semiconductor America Inc, MB15E03SLPFV1-G-BND-6E1 Datasheet - Page 8
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MB15E03SLPFV1-G-BND-6E1
Manufacturer Part Number
MB15E03SLPFV1-G-BND-6E1
Description
SYNTHESIZER PLL 1.2GHZ 16SSOP
Manufacturer
Fujitsu Semiconductor America Inc
Type
Clock/Frequency Synthesizer, Prescalerr
Specifications of MB15E03SLPFV1-G-BND-6E1
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/No
Frequency - Max
1.2GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Frequency-max
1.2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1000-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MB15E03SLPFV1-G-BND-6E1
Manufacturer:
TI
Quantity:
119
8
MB15E03SL
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
f
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider
and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE pin is taken high, stored
data is latched according to the control bit data as follows:
Table 1. Control Bit
(1) Shift Register Configuration
VCO
LSB
CNT R1
FUNCTIONAL DESCRIPTION
= [(M
CNT
R1 to R14
SW
FC
LDS
CS
Note: Start data input with MSB first.
1
f
N
A
f
R
M
VCO
OSC
Programmable Reference Counter
Control Bit (CNT)
2
N) + A]
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
: Preset divide ratio of the dual modulus prescaler (64 or 128)
R2
H
L
3
: Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/fout signal select bit
: Charge pump current select bit
: Control bit
R3
f
OSC
4
R4
R (A < N)
5
R5
6
For the programmable reference divider
For the programmable divider
R6
7
R7
8
Data Flow
R8
9
R9 R10 R11 R12 R13 R14 SW FC
10
Destination of Serial Data
11
12
A
13
127)
14
15
16
17
[Table 1]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
LDS
18
MSB
CS
19