ICS650G-36LFT IDT, Integrated Device Technology Inc, ICS650G-36LFT Datasheet - Page 3

• Manufacturer Part Number: ICS650G-36LFT
• Description: IC CLOCK NETWORK/PCI 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS650G-36LFT

• Pll: Yes with Bypass
• Input: Clock, Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 650G-36LFT

External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS650-36 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20 .
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
pF)*2. In this equation, C
IDT™ / ICS™ NETWORKING AND PCI CLOCK SOURCE
ICS650-36
NETWORKING AND PCI CLOCK SOURCE
Number
Pin
14
15
16
L
= crystal load capacitance in pF.
Name
GND
VDD
REF
Pin
Output
Power
Power
Type
Pin
Reference 25 MHz clock output. Weak internal pull-down when
tri-state.
Connect to ground.
Connect to +3.3 V.
L
-6
3
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
PCB Layout Recommendations
Observed the following guidelines for optimum device
performance and lowest output phase noise:
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitors and VDD pins. The PCB trace to VDD pins
should be kept as short as possible, as should the PCB
trace to the ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) Place the 33 series termination resistor (if needed)
close to the clock output to minimize EMI.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS650-36. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Pin Description
CLOCK SYNTHESIZER
ICS650-36
REV F 051310