MPC9658ACR2 IDT, Integrated Device Technology Inc, MPC9658ACR2 Datasheet
MPC9658ACR2
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MPC9658ACR2 Summary of contents
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LVCMOS PLL CLOCK GENERATOR 3.3 V 1:10 LVCMOS PLL Clock Generator The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR V CC PCLK 25 k PCLK 25 k FB_IN 3⋅25 k PLL_EN VCO_SEL BYPASS MR/ VCO_SEL IDT™ / ICS™ 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR ÷ ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configurations Number Name PCLK, PCLK Input FB_IN Input VCO_SEL Input BYPASS Input PLL_EN Input MR/OE Input Q0–9 Output QFB Output GND Supply V Supply CC_PLL V Supply CC Table 2. ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 4. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch-Up Immunity C Power Dissipation Capacitance PD C Input Capacitance ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 6. AC Characteristics (V CC Symbol f Input reference frequency REF PLL mode, external feedback Input reference frequency in PLL bypass mode f VCO lock frequency range VCO f Output Frequency MAX ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Programming the MPC9658 The MPC9658 supports output clock frequencies from 50 to 250 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Calculation of Part-to-Part Skew The MPC9658 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9658 are ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR MPC958 Output Buffer = 36 Ω Ω In MPC958 Output = 36 Ω R Buffe S 14 Ω Ω Figure 6. Single versus Dual Transmission ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output-to-Output Skew ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR D1 D1/2 PIN 1 INDEX E1 D/2 4X 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ (S) ...
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MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...