ICS650R-14ILF IDT, Integrated Device Technology Inc, ICS650R-14ILF Datasheet - Page 3

• Manufacturer Part Number: ICS650R-14ILF
• Description: IC NETWORKING SYSTEM CLK 20-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS650R-14ILF

• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:7
• Differential - Input:output: No/No
• Frequency - Max: 133.33MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 650R-14ILF

External Components
The ICS650-14 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50 trace (a commonly used trace
impedance) place a 33 resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20 .
IDT™ / ICS™ NETWORKING SYSTEM CLOCK
Number
ICS650-14
NETWORKING SYSTEM CLOCK
Pin
13
14
15
16
17
18
19
20
Key: XI, XO = crystal connections; I = input; I(Pu) = input with pull-up; O = output; P = power supply connection; TI
= tri-level input
CLKA4
SELA1
CLKA3
CLKA2
SELA0
Name
SELC
GND
VDD
Pin
Type
Pin
TI
TI
TI
O
O
O
P
P
Selectable clock output. See table 1.
Connect to ground.
Select pin for CLKA1:4 and CLKA5 outputs. See table 1.
Connect to 3.3 Vor 5 V. Must be same as other VDDs.
Selectable clock output. See table 1.
Selectable clock output. See table 1.
Select pin for CLKA1:4 and CLKA5 outputs. See table 1.
Select pin for CLKC output. See table 3.
3
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
In the equation, C
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Crystal caps (pF) = (C
Pin Description
L
is the crystal load capacitance. For a
L
- 6) x 2
ICS650-14
CLOCK SYNTHESIZER
REV H 051310