ICS673M-01ILF IDT, Integrated Device Technology Inc, ICS673M-01ILF Datasheet - Page 5

• Manufacturer Part Number: ICS673M-01ILF
• Description: IC PLL BUILDING BLOCK 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Phase Lock Loop (PLL)r

Specifications of ICS673M-01ILF

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 120MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Frequency-max: 120MHz
• Number Of Elements: 1
• Supply Current: 15mA
• Pll Input Freq (min): 1KHz
• Pll Input Freq (max): 8MHz
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC N
• Output Frequency Range: 0.25 to 120MHz
• Operating Supply Voltage (min): 3.13V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 673M-01ILF

MDS 673-01 L
increases the VCO frequency. The feedback divider
begins to miss even more clock edges and the VCO
frequency is continually increased until it is running at
its maximum frequency. Whether caused by power
supply issues or by the external divider, the loop can
only recover by powering down the circuit or asserting
PD.
The simplest way to avoid this problem is to use an
external divider that always operates correctly
regardless of the VCO speed. Figures 2 and 3 show
that the VCO is capable of high speeds. By using the
internal divide-by-four and/or the CLK2 output, the
maximum VCO frequency can be divided by 2, 4, or 8
and a slower counter can be used. Using the ICS673
internal dividers in this manner does reduce the
number of frequencies that can be exactly synthesized
by forcing the total VCO divide to change in increments
of 2, 4, or 8.
If this lockup problem occurs, there are several
solutions; three of which are described below.
1. If the system has a reset or power good signal, this
should be applied to the PD pin, forcing the chip to stay
powered down until the power supply voltage has
stabilized
2. If no power good signal is available, a simple
power-on reset circuit can be attached to the PD pin, as
shown in Figure 1. When the power supply ramps up,
this circuit holds PD asserted (device powered down)
until the capacitor charges.
w w w. i d t . c o m
5
The circuit of Figure 1A is adequate in most cases, but
the discharge rate of capacitor C3 when VDD goes low
is limited by R1. As this discharge rate determines the
minimum reset time, the circuit of Figure 1B may be
used when a faster reset time is desired. The values of
R1 and C3 should be selected to ensure that PD stays
below 1.0 V until the power supply is stable.
3. A comparator circuit may be used to monitor the loop
filter voltage as shown in Figure 2. This circuit will dump
the charge off the loop filter by asserting PD if the VCO
begins to run too fast and the PLL can recover. A good
choice for the comparator is the National
Semiconductor LMC7211BIM5X. It is low power,
version of the small (SOT-23), low cost, and has high
input impedance.
The trigger voltage of the comparator is set by the
voltage divider formed by R2 and R3. The voltage
should be set to a value higher than the VCO input is
expected to run during normal operation. Typically, this
Fi g 1 . Po we r o n Re s e t Ci r c u i t s
I CS673- 01
I C S 6 7 3 - 0 1
A. Basi c Ci r cui t
B . F a s t e r D i s c h a r g e
P D
PD
V D D
VDD
PLL B
R
C
R
C
1
3
1
3
UILDING
Revision 051310
D
1
ICS673-01
B
LOCK