ICS87946AYI-01LF IDT, Integrated Device Technology Inc, ICS87946AYI-01LF Datasheet - Page 9

• Manufacturer Part Number: ICS87946AYI-01LF
• Description: IC CLOCK GENERATOR 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Clock Generatorr

Specifications of ICS87946AYI-01LF

• Pll: No
• Input: CML, LVPECL, SSTL
• Output: LVCMOS, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 87946AYI-01LF

Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER
ICS87946I-01
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
DD
= 3.3V, V_REF should be 1.25V and
DD
/2 is
9
O
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
Figure 1. Single-Ended Signal Driving Differential Input
UTPUTS
Single Ended Clock Input
:
C1
0.1u
V_REF
ICS87946AYI-01 REV. BMAY 4, 2007
R1
1K
R2
1K
V
DD
PCLK
nPCLK