MPC9774AE IDT, Integrated Device Technology Inc, MPC9774AE Datasheet - Page 7

• Manufacturer Part Number: MPC9774AE
• Description: IC PLL CLK GEN 1:14 3.3V 52-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9774AE

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 3.3V 1:14 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9774
3.3V 1:14 LVCMOS PLL Clock Generator
Using the MPC9774 in zero-delay applications
MPC9774. Designs using the MPC9774 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback of the
MPC9774 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
l o n g - t e r m j i t t e r ) , f e e d b a c k p a t h d e l a y a n d t h e
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9774 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from
TIMING SOLUTIONS
Nested clock trees are typical applications for the
The MPC9774 zero delay buffer supports applications
This maximum timing uncertainty consist of 4
Due to the statistical nature of I/O jitter a rms value (1 σ) is
t
SK(PP)
Figure 5. MPC9774 max. device-to-device skew
= t
( ∅)
+ t
SK(O)
Table
∅
±t
+ t
10.
∅
PD, LINE(FB)
∅
Freescale Semiconductor, Inc.
For More Information On This Product,
∅
+ t
±t
JIT( ∅)
Go to: www.freescale.com

CF
7
7
layout and can be used to fine-tune the effective delay
through each device.
offset and I/O jitter, using Figure 6 and Figure 7 to predict a
maximum I/O jitter and the specified t
the input reference frequency results in a precise timing
performance analysis.
factor of 99.7% (± 3σ) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of -470 ps to +320 ps relative to CCLK (PLL
feedback = B8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 15 ps rms max., static
phase offset t
t
t
SK(PP)
SK(PP)
Table 10. Confidence factor CF
The feedback trace delay is determined by the board
Due to the frequency dependence of the static phase
In the following example calculation a I/O jitter confidence
± 1s
± 2s
± 3s
± 4s
± 5s
± 6s
CF
=
=
÷
÷
÷
Probability of clock edge within the distribution
(
∅
[–250 ps...+100 ps] + [–175 ps...175 ps] +
[(15 ps
[–470 ps...+320 ps] + t
Figure 6. MPC9774 I/O Jitter
Figure 7. MPC9774 I/O Jitter
)
= –250 ps to +100 ps):
÷
÷
÷
⋅
–3)...(15 ps
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
(
∅
⋅
3)] + t
)
PD, LINE(FB)
parameter relative to
PD, LINE(FB)
MPC9774
MOTOROLA
NETCOM
MPC9774