MPC9855VM IDT, Integrated Device Technology Inc, MPC9855VM Datasheet - Page 8

• Manufacturer Part Number: MPC9855VM
• Description: IC PLL CLOCK GENERATOR 100MAPBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9855VM

• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9855
Clock Generator for PowerQUICC III
8
Table 9. AC Characteristics (V
MPC9855
Input and Output Timing Specification
PLL Specifications
Skew and Jitter Specifications
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to V
3. In bypass mode, the MPC9855 divides the input reference clock.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f
t
reset_pulse
Symbol
t
t
t
JIT(PER)
reset_ref
f
t
f
t
JIT(CC)
t
t
f
f
refPW
refCcc
JIT(∅)
LOCK
t
sk(O)
sk(O)
t
VCO
MCX
DC
f
r
r
ref
, t
, t
f
f
Input Reference Frequency (25 MHz input)
Input Reference Frequency (33 MHz input)
XTAL Input
Input Reference Frequency in PLL Bypass Mode
VCO Frequency Range
Output Frequency
Reference Input Pulse Width
Input Frequency Accuracy
Output Rise/Fall Time
Output Duty Cycle
Maximum PLL Lock Time
MR Hold Time on Power Up
MR Hold Time
Output-to-Output Skew (within a bank)
Output-to-Output Skew (across banks A and B)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Output Rise/Fall Time
Generator
Z = 50Ω
Pulse
Characteristics
DD
Figure 4. MPC9855 AC Test Reference (LVCMOS Outputs)
= 3.3 V ± 5%, V
(4)
Z
V
O
TT
= 50Ω
R
T
= 50Ω
Bank A output
Bank B output
DDOAB
RMS (1 σ)
= 3.3 V ± 5%, T
(3)
TT
8
DUT MPC9855
.
15.87
15.87
Min
150
43
10
10
2
A
= –40°C to +85°C)
2000
Typ
25
33
25
50
Z
O
R
= 50Ω
T
= 50Ω
TBD
Max
250
200
200
100
500
400
200
200
57
10
50
50
(1) (2)
Advanced Clock Drivers Devices
ref
V
TT
= (f
Freescale Semiconductor
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ppm
ms
ps
ns
ns
ns
ps
ps
ps
ps
ps
ns
%
VCO
÷ M) ⋅ N.
PLL bypass
PLL locked
20% to 80%
Bank A and B
V
V
Bank A and B
Bank A and B
Bank A and B
20% to 80%
DDOA
DDOB
Condition
= 3.3 V
= 3.3 V
NETCOM
MPC9855